X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/83967730302e16c0064401c77a8fe54c9d6cd94f..b98e21a53a485e26aca52a3b8c9e0406c25f3ab0:/ethernet/source/pci/pci_user_constants.v

diff --git a/ethernet/source/pci/pci_user_constants.v b/ethernet/source/pci/pci_user_constants.v
index 70c9b0e..af419f1 100644
--- a/ethernet/source/pci/pci_user_constants.v
+++ b/ethernet/source/pci/pci_user_constants.v
@@ -143,8 +143,8 @@
 
 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
 // output buffers instantiated. Xilinx FPGAs use active low output enables.
-// `define ACTIVE_LOW_OE
-`define ACTIVE_HIGH_OE
+`define ACTIVE_LOW_OE
+//`define ACTIVE_HIGH_OE
 
 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
 // only one can be defined at same time