X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/8d57b1fba1724af67d6bc884e787ae67ffd99d48..e00b64cc5780386174db7506cad5bccee09087b0:/ethernet/ethernet.prj

diff --git a/ethernet/ethernet.prj b/ethernet/ethernet.prj
new file mode 100644
index 0000000..5bd7d4e
--- /dev/null
+++ b/ethernet/ethernet.prj
@@ -0,0 +1,28 @@
+vhdl work "source/top.vhd"
+verilog work "source/ethernet/eth_crc.v"
+verilog work "source/ethernet/eth_cop.v"
+verilog work "source/ethernet/eth_maccontrol.v"
+verilog work "source/ethernet/eth_register.v"
+verilog work "source/ethernet/eth_fifo.v"
+verilog work "source/ethernet/eth_rxstatem.v"
+verilog work "source/ethernet/eth_txcounters.v"
+verilog work "source/ethernet/eth_random.v"
+verilog work "source/ethernet/eth_rxcounters.v"
+verilog work "source/ethernet/eth_top.v"
+verilog work "source/ethernet/eth_shiftreg.v"
+verilog work "source/ethernet/eth_miim.v"
+verilog work "source/ethernet/eth_wishbone.v"
+verilog work "source/ethernet/eth_rxaddrcheck.v"
+verilog work "source/ethernet/xilinx_dist_ram_16x32.v"
+verilog work "source/ethernet/eth_spram_256x32.v"
+verilog work "source/ethernet/eth_txethmac.v"
+verilog work "source/ethernet/timescale.v"
+verilog work "source/ethernet/eth_registers.v"
+verilog work "source/ethernet/eth_defines.v"
+verilog work "source/ethernet/eth_rxethmac.v"
+verilog work "source/ethernet/eth_receivecontrol.v"
+verilog work "source/ethernet/eth_outputcontrol.v"
+verilog work "source/ethernet/eth_txstatem.v"
+verilog work "source/ethernet/eth_transmitcontrol.v"
+verilog work "source/ethernet/eth_macstatus.v"
+verilog work "source/ethernet/eth_clockgen.v"