X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/95764a116fa3408e586d0e77d413b56449a7f457..2a7d0ce665689e7d493d3c613e6d02dda135a979:/heartbeat/source/top_raggedstone.vhd diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd index 6b449a7..3d369cf 100644 --- a/heartbeat/source/top_raggedstone.vhd +++ b/heartbeat/source/top_raggedstone.vhd @@ -38,12 +38,13 @@ use ieee.std_logic_unsigned.all; --| ENTITY | --+-----------------------------------------------------------------------------+ -entity pci_7seg is +entity raggedstone is port ( -- General PCI_CLK : in std_logic; PCI_nRES : in std_logic; + PCI_nREQ : out std_logic; -- PCI target 32bits PCI_AD : inout std_logic_vector(31 downto 0); @@ -59,30 +60,25 @@ port ( PCI_nSERR : out std_logic; PCI_nINT : out std_logic; - -- 7seg - DISP_SEL : inout std_logic_vector(3 downto 0); - DISP_LED : out std_logic_vector(6 downto 0); - -- debug signals - LED_INIT : out std_logic; - LED_ACCESS : out std_logic; - LED_ALIVE : out std_logic; - - -- vga signals - hs : out std_logic; - vs : out std_logic; - red, grn, blu : out std_logic; - mclk : in std_logic + LED3 : out std_logic; + LED2 : out std_logic; + LED4 : out std_logic; + LED5 : out std_logic; + IDE1 : out std_logic; + IDE2 : out std_logic; + IDE3 : out std_logic; + IDE4 : out std_logic ); -end pci_7seg; +end raggedstone; --+-----------------------------------------------------------------------------+ --| ARCHITECTURE | --+-----------------------------------------------------------------------------+ -architecture pci_7seg_arch of pci_7seg is +architecture raggedstone_arch of raggedstone is --+-----------------------------------------------------------------------------+ @@ -129,41 +125,19 @@ port ( ); end component; - -component wb_7seg_new +component heartbeat port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - - -- Master whisbone - wb_adr_i : in std_logic_vector(24 downto 1); - wb_dat_o : out std_logic_vector(15 downto 0); - wb_dat_i : in std_logic_vector(15 downto 0); - wb_sel_i : in std_logic_vector(1 downto 0); - wb_we_i : in std_logic; - wb_stb_i : in std_logic; - wb_cyc_i : in std_logic; - wb_ack_o : out std_logic; - wb_err_o : out std_logic; - wb_int_o : out std_logic; - - -- 7seg - DISP_SEL : inout std_logic_vector(3 downto 0); - DISP_LED : out std_logic_vector(6 downto 0) - - ); -end component; - - -component vgaController is - Port ( mclk : in std_logic; - hs : out std_logic; - vs : out std_logic; - red : out std_logic; - grn : out std_logic; - blu : out std_logic); + clk_i : in std_logic; + nrst_i : in std_logic; + led2_o : out std_logic; + led3_o : out std_logic; + led4_o : out std_logic; + led5_o : out std_logic; + led6_o : out std_logic; + led7_o : out std_logic; + led8_o : out std_logic; + led9_o : out std_logic +); end component; @@ -188,17 +162,7 @@ end component; begin - LED_ALIVE <= '1'; ---+-------------------------------------------------------------------------+ ---| Component instances | ---+-------------------------------------------------------------------------+ - - vga1: vgaController port map (mclk => mclk, - hs => hs, - vs => vs, - red => red, - grn => grn, - blu => blu); + PCI_nREQ <= '1'; --+-----------------------------------------+ --| PCI Target | @@ -229,31 +193,27 @@ port map( wb_cyc_o => wb_cyc, wb_ack_i => wb_ack, wb_err_i => wb_err, - wb_int_i => wb_int, - debug_init => LED_INIT, - debug_access => LED_ACCESS + wb_int_i => wb_int +-- debug_init => LED3, +-- debug_access => LED2 ); --+-----------------------------------------+ --| WB-7seg | --+-----------------------------------------+ -u_wb: component wb_7seg_new -port map( - clk_i => PCI_CLK, - nrst_i => PCI_nRES, - wb_adr_i => wb_adr, - wb_dat_o => wb_dat_out, - wb_dat_i => wb_dat_in, - wb_sel_i => wb_sel, - wb_we_i => wb_we, - wb_stb_i => wb_stb, - wb_cyc_i => wb_cyc, - wb_ack_o => wb_ack, - wb_err_o => wb_err, - wb_int_o => wb_int, - DISP_SEL => DISP_SEL, - DISP_LED => DISP_LED +my_heartbeat: component heartbeat +port map( + clk_i => PCI_CLK, + nrst_i => PCI_nRES, + led2_o => LED2, + led3_o => LED3, + led4_o => LED4, + led5_o => LED5, + led6_o => IDE1, + led7_o => IDE2, + led8_o => IDE3, + led9_o => IDE4 ); -end pci_7seg_arch; +end raggedstone_arch;