X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/a76e12bdfc68f955f1cedd0c928fba9372a55d07..30273618403fd6512926c89f999f97b4722e1709:/dhwk/source/top.vhd?ds=sidebyside

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
deleted file mode 100644
index e2f307c..0000000
--- a/dhwk/source/top.vhd
+++ /dev/null
@@ -1,383 +0,0 @@
--- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
-
-
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity dhwk is
-      Port ( KONST_1 : In    std_logic;
-             PCI_CBEn : In    std_logic_vector (3 downto 0);
-             PCI_CLOCK : In    std_logic;
-             PCI_FRAMEn : In    std_logic;
-             PCI_IDSEL : In    std_logic;
-             PCI_IRDYn : In    std_logic;
-             PCI_RSTn : In    std_logic;
---             SERIAL_IN : In    std_logic;
---             SPC_RDY_IN : In    std_logic;
-             TAST_RESn : In    std_logic;
-             TAST_SETn : In    std_logic;
-             LED_2 : out    std_logic;
-             LED_3 : out    std_logic;
-             LED_4 : out    std_logic;
-             LED_5 : out    std_logic;
-              PCI_AD : InOut std_logic_vector (31 downto 0);
-             PCI_PAR : InOut std_logic;
-             PCI_DEVSELn : Out   std_logic;
-             PCI_INTAn : Out   std_logic;
-             PCI_PERRn : Out   std_logic;
-             PCI_SERRn : Out   std_logic;
-             PCI_STOPn : Out   std_logic;
-             PCI_TRDYn : Out   std_logic;
---             SERIAL_OUT : Out   std_logic;
---             SPC_RDY_OUT : Out   std_logic;
-             TB_IDSEL : Out   std_logic;
-             TB_nDEVSEL : Out   std_logic;
-             TB_nINTA : Out   std_logic );
-end dhwk;
-
-architecture SCHEMATIC of dhwk is
-
-   SIGNAL gnd : std_logic := '0';
-   SIGNAL vcc : std_logic := '1';
-
-   signal READ_XX7_6 : std_logic;
-   signal  RESERVE : std_logic;
-   signal SR_ERROR : std_logic;
-   signal  R_ERROR : std_logic;
-   signal  S_ERROR : std_logic;
-   signal WRITE_XX3_2 : std_logic;
-   signal WRITE_XX5_4 : std_logic;
-   signal WRITE_XX7_6 : std_logic;
-   signal READ_XX1_0 : std_logic;
-   signal READ_XX3_2 : std_logic;
-   signal    INTAn : std_logic;
-   signal    TRDYn : std_logic;
-   signal READ_XX5_4 : std_logic;
-   signal  DEVSELn : std_logic;
-   signal FIFO_RDn : std_logic;
-   signal WRITE_XX1_0 : std_logic;
-   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
-   signal SYNC_FLAG : std_logic_vector (7 downto 0);
-   signal  INT_REG : std_logic_vector (7 downto 0);
-   signal REVISON_ID : std_logic_vector (7 downto 0);
-   signal VENDOR_ID : std_logic_vector (15 downto 0);
-   signal READ_SEL : std_logic_vector (1 downto 0);
-   signal   AD_REG : std_logic_vector (31 downto 0);
-   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
-   signal R_EFn : std_logic;
-   signal R_FFn : std_logic;
-   signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
-   signal R_HFn : std_logic;
-   signal S_EFn : std_logic;
-   signal S_FFn : std_logic;
-   signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
-   signal S_HFn : std_logic;
-   signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
-   signal R_FIFO_READn : std_logic;
-   signal R_FIFO_RESETn : std_logic;
-   signal R_FIFO_RTn : std_logic;
-   signal R_FIFO_WRITEn : std_logic;
-   signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
-   signal S_FIFO_READn : std_logic;
-   signal S_FIFO_RESETn : std_logic;
-   signal S_FIFO_RTn : std_logic;
-   signal S_FIFO_WRITEn : std_logic;
-   signal SERIAL_IN : std_logic;
-   signal SPC_RDY_IN : std_logic;
-   signal SERIAL_OUT : std_logic;
-   signal SPC_RDY_OUT : std_logic;
-   signal watch : std_logic;
-   signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(35 downto 0);
-   signal trig0      : std_logic_vector(7 downto 0);
-
-   component MESS_1_TB
-      Port ( DEVSELn : In    std_logic;
-               INTAn : In    std_logic;
-             KONST_1 : In    std_logic;
-             PCI_IDSEL : In    std_logic;
-             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);
-             TB_DEVSELn : Out   std_logic;
-             TB_INTAn : Out   std_logic;
-             TB_PCI_IDSEL : Out   std_logic );
-   end component;
-
-   component VEN_REV_ID
-      Port (  REV_ID : Out   std_logic_vector (7 downto 0);
-              VEN_ID : Out   std_logic_vector (15 downto 0) );
-   end component;
-
-   component INTERRUPT
-      Port ( INT_IN_0 : In    std_logic;
-             INT_IN_1 : In    std_logic;
-             INT_IN_2 : In    std_logic;
-             INT_IN_3 : In    std_logic;
-             INT_IN_4 : In    std_logic;
-             INT_IN_5 : In    std_logic;
-             INT_IN_6 : In    std_logic;
-             INT_IN_7 : In    std_logic;
-             INT_MASKE : In    std_logic_vector (7 downto 0);
-             INT_RES : In    std_logic_vector (7 downto 0);
-             PCI_CLOCK : In    std_logic;
-             PCI_RSTn : In    std_logic;
-             READ_XX5_4 : In    std_logic;
-               RESET : In    std_logic;
-             TAST_RESn : In    std_logic;
-             TAST_SETn : In    std_logic;
-               TRDYn : In    std_logic;
-             INT_REG : Out   std_logic_vector (7 downto 0);
-               INTAn : Out   std_logic;
-             PCI_INTAn : Out   std_logic );
-   end component;
-
-   component FIFO_CONTROL
-      Port ( FIFO_RDn : In    std_logic;
-             FLAG_IN_0 : In    std_logic;
-             FLAG_IN_4 : In    std_logic;
-                HOLD : In    std_logic;
-             KONST_1 : In    std_logic;
-             PCI_CLOCK : In    std_logic;
-             PSC_ENABLE : In    std_logic;
-               R_EFn : In    std_logic;
-               R_FFn : In    std_logic;
-               R_HFn : In    std_logic;
-               RESET : In    std_logic;
-               S_EFn : In    std_logic;
-               S_FFn : In    std_logic;
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
-               S_HFn : In    std_logic;
-             SERIAL_IN : In    std_logic;
-             SPC_ENABLE : In    std_logic;
-             SPC_RDY_IN : In    std_logic;
-             WRITE_XX1_0 : In    std_logic;
-             R_ERROR : Out   std_logic;
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
-             R_FIFO_READn : Out   std_logic;
-             R_FIFO_RESETn : Out   std_logic;
-             R_FIFO_RETRANSMITn : Out   std_logic;
-             R_FIFO_WRITEn : Out   std_logic;
-             RESERVE : Out   std_logic;
-             S_ERROR : Out   std_logic;
-             S_FIFO_READn : Out   std_logic;
-             S_FIFO_RESETn : Out   std_logic;
-             S_FIFO_RETRANSMITn : Out   std_logic;
-             S_FIFO_WRITEn : Out   std_logic;
-             SERIAL_OUT : Out   std_logic;
-             SPC_RDY_OUT : Out   std_logic;
-             SR_ERROR : Out   std_logic;
-	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
-   end component;
-
-   component PCI_TOP
-      Port (    FLAG : In    std_logic_vector (7 downto 0);
-             INT_REG : In    std_logic_vector (7 downto 0);
-             PCI_CBEn : In    std_logic_vector (3 downto 0);
-             PCI_CLOCK : In    std_logic;
-             PCI_FRAMEn : In    std_logic;
-             PCI_IDSEL : In    std_logic;
-             PCI_IRDYn : In    std_logic;
-             PCI_RSTn : In    std_logic;
-             R_FIFO_Q : In    std_logic_vector (7 downto 0);
-             REVISON_ID : In    std_logic_vector (7 downto 0);
-             VENDOR_ID : In    std_logic_vector (15 downto 0);
-              PCI_AD : InOut std_logic_vector (31 downto 0);
-             PCI_PAR : InOut std_logic;
-              AD_REG : Out   std_logic_vector (31 downto 0);
-             DEVSELn : Out   std_logic;
-             FIFO_RDn : Out   std_logic;
-             PCI_DEVSELn : Out   std_logic;
-             PCI_PERRn : Out   std_logic;
-             PCI_SERRn : Out   std_logic;
-             PCI_STOPn : Out   std_logic;
-             PCI_TRDYn : Out   std_logic;
-             READ_SEL : Out   std_logic_vector (1 downto 0);
-             READ_XX1_0 : Out   std_logic;
-             READ_XX3_2 : Out   std_logic;
-             READ_XX5_4 : Out   std_logic;
-             READ_XX7_6 : Out   std_logic;
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
-               TRDYn : Out   std_logic;
-             WRITE_XX1_0 : Out   std_logic;
-             WRITE_XX3_2 : Out   std_logic;
-             WRITE_XX5_4 : Out   std_logic;
-             WRITE_XX7_6 : Out   std_logic );
-   end component;
-
-component fifo_generator_v3_2
-        port (
-        clk: IN std_logic;
-        din: IN std_logic_VECTOR(7 downto 0);
-        rd_en: IN std_logic;
-        rst: IN std_logic;
-        wr_en: IN std_logic;
-        almost_empty: OUT std_logic;
-        almost_full: OUT std_logic;
-        dout: OUT std_logic_VECTOR(7 downto 0);
-        empty: OUT std_logic;
-        full: OUT std_logic;
-        prog_full: OUT std_logic);
-end component;
-
-component icon
-port
-	(
-	 control0    :   out std_logic_vector(35 downto 0)
-	);
-end component;
-
-  component ila
-    port
-    (
-      control     : in    std_logic_vector(35 downto 0);
-      clk         : in    std_logic;
-      data        : in    std_logic_vector(35 downto 0);
-      trig0       : in    std_logic_vector(7 downto 0)
-    );
-  end component;
-
-
-begin
-	SERIAL_IN <= SERIAL_OUT;
-	SPC_RDY_IN <= SPC_RDY_OUT;
-	LED_2 <= TAST_RESn;
-	LED_3 <= TAST_SETn;
-	LED_4 <= '0';
-	LED_5 <= not watch;
-	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, others => '0');
-	data(0) <= watch;
-	
-	data(1) <= R_EFn;
-	data(2) <= R_HFn;
-	data(3) <= R_FFn;
-	data(4) <= R_FIFO_READn;
-	data(5) <= R_FIFO_RESETn;
-	data(6) <= R_FIFO_RTn;
-	data(7) <= R_FIFO_WRITEn;
-	data(8) <= S_EFn;
-	data(9) <= S_HFn;
-	data(10) <= S_FFn;
-	data(11) <= S_FIFO_READn;
-	data(12) <= S_FIFO_RESETn;
-	data(13) <= S_FIFO_RTn;
-	data(14) <= S_FIFO_WRITEn;
-	data(15) <= SERIAL_IN;
-	data(16) <= SPC_RDY_IN;
-	data(17) <= SERIAL_OUT;
-	data(18) <= SPC_RDY_OUT;
-
-   I19 : MESS_1_TB
-      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
-                 PCI_IDSEL=>PCI_IDSEL,
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
-                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
-                 TB_PCI_IDSEL=>TB_IDSEL );
-   I18 : VEN_REV_ID
-      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
-                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
-   I16 : INTERRUPT
-      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
-                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
-                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
-                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
-                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
-                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
-                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
-                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
-                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 INTAn=>INTAn, PCI_INTAn=>watch);
-   I14 : FIFO_CONTROL
-      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
-                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
-                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
-                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
-                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
-                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
-                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
-                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
-                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
-                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
-                 R_FIFO_READn=>R_FIFO_READn,
-                 R_FIFO_RESETn=>R_FIFO_RESETn,
-                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
-                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
-                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
-                 S_FIFO_RESETn=>S_FIFO_RESETn,
-                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
-                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
-                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
-		 PAR_SER_IN(7 downto 0)=>data(26 downto 19),
-                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
-   I1 : PCI_TOP
-      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
-                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
-                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
-                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
-                 PCI_RSTn=>PCI_RSTn,
-                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
-                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
-                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
-                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
-                 PCI_PAR=>PCI_PAR,
-                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
-                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
-                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
-                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
-                 PCI_TRDYn=>PCI_TRDYn,
-                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
-                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
-                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
-                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
-                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
-                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
-                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
-                 WRITE_XX7_6=>WRITE_XX7_6 );
-
-receive_fifo : fifo_generator_v3_2
-                port map (
-                        clk => PCI_CLOCK,
-                        din => R_FIFO_D_IN,
-                        rd_en => not R_FIFO_READn,
-                        rst => not R_FIFO_RESETn,
-                        wr_en => not R_FIFO_WRITEn,
-                        dout => R_FIFO_Q_OUT,
-                        empty => R_EFn,
-                        full => R_FFn,
-                        prog_full => R_HFn);
-
-send_fifo : fifo_generator_v3_2
-                port map (
-                        clk => PCI_CLOCK,
-                        din => S_FIFO_D_IN,
-                        rd_en => not S_FIFO_READn,
-                        rst => not S_FIFO_RESETn,
-                        wr_en => not S_FIFO_WRITEn,
-                        dout => S_FIFO_Q_OUT,
-                        empty => S_EFn,
-                        full => S_FFn,
-                        prog_full => S_HFn);
-
-  i_icon : icon
-      port map
-          (
-	        control0    => control0
-	  );
-
-  i_ila : ila
-    port map
-    (
-      control   => control0,
-      clk       => PCI_CLOCK,
-      data      => data,
-      trig0     => trig0
-    );
-end SCHEMATIC;