X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/a76e12bdfc68f955f1cedd0c928fba9372a55d07..8985684ba1f0b0006387e6a45ec44f684bce0d36:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c..971b0c4 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(35 downto 0);
-   signal trig0      : std_logic_vector(7 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -169,7 +169,6 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
-	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
    end component;
 
@@ -237,8 +236,8 @@ end component;
     (
       control     : in    std_logic_vector(35 downto 0);
       clk         : in    std_logic;
-      data        : in    std_logic_vector(35 downto 0);
-      trig0       : in    std_logic_vector(7 downto 0)
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
     );
   end component;
 
@@ -251,7 +250,7 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, others => '0');
+	trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
 	data(0) <= watch;
 	
 	data(1) <= R_EFn;
@@ -272,6 +271,10 @@ begin
 	data(16) <= SPC_RDY_IN;
 	data(17) <= SERIAL_OUT;
 	data(18) <= SPC_RDY_OUT;
+	data(26 downto 19) <= S_FIFO_Q_OUT;
+	data(34 downto 27) <= R_FIFO_Q_OUT;
+	data(66 downto 35) <= PCI_AD(31 downto 0);
+	data(70 downto 67) <= PCI_CBEn(3 downto 0);
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -313,7 +316,6 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
-		 PAR_SER_IN(7 downto 0)=>data(26 downto 19),
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
    I1 : PCI_TOP
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),