X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/ac5b827129ac002c0b2caa0d822868383c1416f2..a93ef3acf570a7f2bd850608f286510d291a199d:/ethernet/source/top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 480de0a..f7c5bd9 100644
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -175,7 +175,6 @@ component phydcm is
 port ( CLKIN_IN        : in    std_logic;
        RST_IN          : in    std_logic;
        CLKFX_OUT       : out   std_logic;
-       CLKIN_IBUFG_OUT : out   std_logic;
        CLK0_OUT        : out   std_logic;
        LOCKED_OUT      : out   std_logic);
 end component;
@@ -231,6 +230,7 @@ signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
+signal mdc_pad_o_watch : std_logic;
 
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
@@ -269,11 +269,20 @@ wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 wb_clk_i <= PCI_CLOCK;
 
 data(31 downto 0)  <= wbm_adr_o;
-data(40 downto 33) <= wbm_adr_o (7 downto 0);
-data(63 downto 41) <= (others => '0');
+data(39 downto 32) <= wbm_adr_o (7 downto 0);
+data(40) <= MD_PAD_IO;
+data(41) <= md_pad_o;
+data(42) <= md_padoe_o;
+data(43) <= mdc_pad_o_watch;
+data(44) <= pci_inta_o;
+MDC_PAD_O <= mdc_pad_o_watch;
+data(63 downto 45) <= (others => '0');
 
 trig0(31 downto 0) <= (
 	0 => wb_stb_i,
+	1 => MD_PAD_IO,
+	2 => md_pad_o,
+	3 => md_padoe_o,
 	others => '0'
 );
 
@@ -380,7 +389,7 @@ Inst_eth_top: eth_top PORT MAP(
         mrxerr_pad_i => MRXERR_PAD_I,
         mcoll_pad_i => MCOLL_PAD_I,
         mcrs_pad_i => MCRS_PAD_I,
-        mdc_pad_o => MDC_PAD_O,
+        mdc_pad_o => mdc_pad_o_watch,
         md_pad_i => MD_PAD_IO,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
@@ -406,10 +415,9 @@ eth_dcm : phydcm
 port map (
 	CLKIN_IN => PCI_CLOCK,
 	RST_IN => not PCI_RSTn,
-	CLKFX_OUT => PHY_CLOCK
---	CLKIN_IBUFG_OUT
---	CLK0_OUT
---	LOCKED_OUT
+	CLKFX_OUT => PHY_CLOCK,
+	CLK0_OUT => open,
+	LOCKED_OUT => open
 	);
 
 end architecture ethernet_arch;