X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/ad16d1e3db67bf7bf820254517c1df11f2db5569..36a53ce255c40f7051820ffbaaac1dd646a83bfb:/heartbeat/source/top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 2834959..c798294 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -60,9 +60,14 @@ port (
     PCI_nINT    : out std_logic;
  
 	-- debug signals
-	LED_INIT	 : out std_logic;
-	LED_ACCESS	 : out std_logic;
-	LED_ALIVE : out std_logic
+	LED3	: out std_logic;
+	LED2	: out std_logic;
+	LED4		: out std_logic;
+	LED5		: out std_logic;
+	IDE1	: out std_logic;
+	IDE2	: out std_logic;
+	IDE3	: out std_logic;
+	IDE4	: out std_logic
 
 );
 end raggedstone;
@@ -123,7 +128,14 @@ component heartbeat
 port (
 	clk_i : in std_logic;
 	nrst_i : in std_logic;
-	led_o : out std_logic
+	led2_o : out std_logic;
+	led3_o : out std_logic;
+	led4_o : out std_logic;
+	led5_o : out std_logic;
+	led6_o : out std_logic;
+	led7_o : out std_logic;
+	led8_o : out std_logic;
+	led9_o : out std_logic
 );
 end component;
 
@@ -178,9 +190,9 @@ port map(
 		wb_cyc_o =>		wb_cyc,
 		wb_ack_i =>		wb_ack,
 		wb_err_i =>		wb_err,
-		wb_int_i =>		wb_int,
-		debug_init =>	LED_INIT,
-		debug_access =>	LED_ACCESS
+		wb_int_i =>		wb_int
+--		debug_init =>	LED3,
+--		debug_access =>	LED2
 		);
 
 --+-----------------------------------------+
@@ -191,7 +203,14 @@ my_heartbeat: component heartbeat
 port map( 
 	clk_i => PCI_CLK,
 	nrst_i => PCI_nRES,
-	led_o => LED_ALIVE
+	led2_o => LED2,
+	led3_o => LED3,
+	led4_o => LED4,
+	led5_o => LED5,
+	led6_o => IDE1,
+	led7_o => IDE2,
+	led8_o => IDE3,
+	led9_o => IDE4
 );
 
 end raggedstone_arch;