X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/bae92bb8f225183e2b73d4723d655675e6375795..1eb920cafb45866e18e34e319ae747af9753665d:/heartbeat/source/heartbeat.vhd

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index 03a465b..03180ef 100644
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -14,7 +14,11 @@ port (
 	led2_o : out std_logic;
 	led3_o : out std_logic;
 	led4_o : out std_logic;
-	led5_o : out std_logic
+	led5_o : out std_logic;
+	led6_o : out std_logic;
+	led7_o : out std_logic;
+	led8_o : out std_logic;
+	led9_o : out std_logic
 );   
 
 end heartbeat;
@@ -23,19 +27,23 @@ architecture rtl of heartbeat is
 begin
 
 process(clk_i, nrst_i)
-variable counter : std_logic_vector(31 downto 0);
-variable state : std_logic_vector(3 downto 0) := "0001";
+variable counter : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
+variable state : std_logic_vector(7 downto 0) := "00000001";
 variable direction : std_logic := '0';
 begin
 
 if (rising_edge(clk_i)) then
-	if nrst_i = '0' then
-		counter := (others => '0');
-        else
+--	if nrst_i = '0' then
+--		counter := (others => '0');
+--        else
 		led2_o <= state(0);
 		led3_o <= state(1);
 		led4_o <= state(2);
 		led5_o <= state(3);
+		led6_o <= state(4);
+		led7_o <= state(5);
+		led8_o <= state(6);
+		led9_o <= state(7);
 		counter := counter + 1;
 		if counter = divider then
 			if state(3) = '1' then
@@ -47,15 +55,15 @@ if (rising_edge(clk_i)) then
 			end if;
 
 			if direction = '0' then
-				state(3 downto 1) := state(2 downto 0);
+				state(7 downto 1) := state(6 downto 0);
 				state(0) := '0';
 			else
-				state(2 downto 0) := state(3 downto 1);
-				state(3) := '0';
+				state(6 downto 0) := state(7 downto 1);
+				state(7) := '0';
 			end if;
 			counter := (others => '0');
 	        end if;
-	end if;
+--	end if;
 end if;
 end process;
 end architecture;