X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/bba7a6d51635a1cb7d31bdfc03b1a66ee9df336b..7b87d14ddc684e6387fea63b0c8551737de13e15:/dhwk/source/top.vhd diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd index a79c470..a148b38 100644 --- a/dhwk/source/top.vhd +++ b/dhwk/source/top.vhd @@ -32,6 +32,8 @@ entity dhwk is PCI_SERRn : Out std_logic; PCI_STOPn : Out std_logic; PCI_TRDYn : Out std_logic; + PCI_REQn : Out std_logic; + PCI_GNTn : In std_logic; -- SERIAL_OUT : Out std_logic; -- SPC_RDY_OUT : Out std_logic; TB_IDSEL : Out std_logic; @@ -90,7 +92,15 @@ architecture SCHEMATIC of dhwk is signal SPC_RDY_IN : std_logic; signal SERIAL_OUT : std_logic; signal SPC_RDY_OUT : std_logic; - signal watch : std_logic; + signal watch_PCI_INTAn : std_logic; + signal watch_PCI_TRDYn : std_logic; + signal watch_PCI_STOPn : std_logic; + signal watch_PCI_SERRn : std_logic; + signal watch_PCI_PERRn : std_logic; + signal watch_PCI_REQn : std_logic; + signal control0 : std_logic_vector(35 downto 0); + signal data : std_logic_vector(95 downto 0); + signal trig0 : std_logic_vector(31 downto 0); component MESS_1_TB Port ( DEVSELn : In std_logic; @@ -206,7 +216,7 @@ architecture SCHEMATIC of dhwk is WRITE_XX7_6 : Out std_logic ); end component; -component fifo_generator_v3_2 +component dhwk_fifo port ( clk: IN std_logic; din: IN std_logic_VECTOR(7 downto 0); @@ -221,14 +231,92 @@ component fifo_generator_v3_2 prog_full: OUT std_logic); end component; +component icon +port + ( + control0 : out std_logic_vector(35 downto 0) + ); +end component; + + component ila + port + ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(95 downto 0); + trig0 : in std_logic_vector(31 downto 0) + ); + end component; + + begin + watch_PCI_REQn <= '1'; SERIAL_IN <= SERIAL_OUT; SPC_RDY_IN <= SPC_RDY_OUT; - LED_2 <= TAST_RESn; - LED_3 <= TAST_SETn; - LED_4 <= '0'; - LED_5 <= not watch; - PCI_INTAn <= watch; + LED_2 <= not PCI_RSTn; + LED_3 <= PCI_IDSEL; + LED_4 <= not PCI_FRAMEn; + LED_5 <= not watch_PCI_INTAn; + PCI_INTAn <= watch_PCI_INTAn; + trig0(31 downto 0) <= ( + 0 => watch_PCI_INTAn, + 1 => R_FIFO_READn, + 2 => R_FIFO_WRITEn, + 3 => S_FIFO_READn, + 4 => S_FIFO_WRITEn, + 5 => PCI_RSTn, + 16 => PCI_AD(0), + 17 => PCI_AD(1), + 18 => PCI_AD(2), + 19 => PCI_AD(3), + 20 => PCI_AD(4), + 21 => PCI_AD(5), + 22 => PCI_AD(6), + 23 => PCI_AD(7), + 27 => PCI_FRAMEn, + 28 => PCI_CBEn(0), + 29 => PCI_CBEn(1), + 30 => PCI_CBEn(2), + 31 => PCI_CBEn(3), + others => '0'); + + data(0) <= watch_PCI_INTAn; + data(1) <= R_EFn; + data(2) <= R_HFn; + data(3) <= R_FFn; + data(4) <= R_FIFO_READn; + data(5) <= R_FIFO_RESETn; + data(6) <= R_FIFO_RTn; + data(7) <= R_FIFO_WRITEn; + data(8) <= S_EFn; + data(9) <= S_HFn; + data(10) <= S_FFn; + data(11) <= S_FIFO_READn; + data(12) <= S_FIFO_RESETn; + data(13) <= S_FIFO_RTn; + data(14) <= S_FIFO_WRITEn; + data(15) <= SERIAL_IN; + data(16) <= SPC_RDY_IN; + data(17) <= SERIAL_OUT; + data(18) <= SPC_RDY_OUT; + data(26 downto 19) <= S_FIFO_Q_OUT; + data(34 downto 27) <= R_FIFO_Q_OUT; + data(66 downto 35) <= PCI_AD(31 downto 0); + data(70 downto 67) <= PCI_CBEn(3 downto 0); + data(71) <= PCI_FRAMEn; + data(72) <= PCI_IDSEL; + PCI_TRDYn <= watch_PCI_TRDYn; + data(73) <= watch_PCI_TRDYn; + data(74) <= PCI_IRDYn; + PCI_STOPn <= watch_PCI_STOPn; + data(75) <= watch_PCI_STOPn; + PCI_SERRn <= watch_PCI_SERRn; + data(76) <= watch_PCI_SERRn; + PCI_PERRn <= watch_PCI_PERRn; + data(77) <= watch_PCI_PERRn; + PCI_REQn <= watch_PCI_REQn; + data(78) <= watch_PCI_REQn; + data(79) <= PCI_GNTn; I19 : MESS_1_TB Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1, @@ -249,7 +337,7 @@ begin READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0), TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn, TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0), - INTAn=>INTAn, PCI_INTAn=>watch); + INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn); I14 : FIFO_CONTROL Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR, FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1, @@ -285,9 +373,9 @@ begin PCI_PAR=>PCI_PAR, AD_REG(31 downto 0)=>AD_REG(31 downto 0), DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn, - PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn, - PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn, - PCI_TRDYn=>PCI_TRDYn, + PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn, + PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn, + PCI_TRDYn=>watch_PCI_TRDYn, READ_SEL(1 downto 0)=>READ_SEL(1 downto 0), READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2, READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6, @@ -298,7 +386,7 @@ begin WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 ); -receive_fifo : fifo_generator_v3_2 +receive_fifo : dhwk_fifo port map ( clk => PCI_CLOCK, din => R_FIFO_D_IN, @@ -310,7 +398,7 @@ receive_fifo : fifo_generator_v3_2 full => R_FFn, prog_full => R_HFn); -send_fifo : fifo_generator_v3_2 +send_fifo : dhwk_fifo port map ( clk => PCI_CLOCK, din => S_FIFO_D_IN, @@ -321,4 +409,19 @@ send_fifo : fifo_generator_v3_2 empty => S_EFn, full => S_FFn, prog_full => S_HFn); + + i_icon : icon + port map + ( + control0 => control0 + ); + + i_ila : ila + port map + ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); end SCHEMATIC;