X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/cb1c44d6708424cf086478148f8cb63a1d2306f0..cf1ee28a524bbda8dbaac7304cf517bb56558470:/dhwk/source/pci/top.vhd

diff --git a/dhwk/source/pci/top.vhd b/dhwk/source/pci/top.vhd
index 01c30b6..86cd575 100644
--- a/dhwk/source/pci/top.vhd
+++ b/dhwk/source/pci/top.vhd
@@ -97,8 +97,10 @@ architecture SCHEMATIC of dhwk is
         signal watch_PCI_PERRn : std_logic;
         signal watch_PCI_REQn : std_logic;
         signal control0 : std_logic_vector(35 downto 0);
+        signal control1 : std_logic_vector(35 downto 0);
         signal data : std_logic_vector(95 downto 0);
         signal trig0 : std_logic_vector(31 downto 0);
+	signal vio_async_out : std_logic_vector(0 downto 0);
 
         component MESS_1_TB
                 Port ( DEVSELn : In std_logic;
@@ -232,7 +234,8 @@ architecture SCHEMATIC of dhwk is
         component icon
                 port
                 (
-                        control0 : out std_logic_vector(35 downto 0)
+                        control0 : out std_logic_vector(35 downto 0);
+                        control1 : out std_logic_vector(35 downto 0)
                 );
         end component;
 
@@ -246,6 +249,14 @@ architecture SCHEMATIC of dhwk is
                 );
         end component;
 
+	component vio
+		port
+		(
+			control : in std_logic_vector(35 downto 0);
+			async_out : out std_logic_vector(0 downto 0)
+		);
+	end component;
+
 
 begin
         watch_PCI_REQn <= '1';
@@ -255,7 +266,8 @@ begin
         LED_3 <= not PCI_IDSEL;
         LED_4 <= not PCI_FRAMEn;
         LED_5 <= not watch_PCI_INTAn;
-        PCI_INTAn <= watch_PCI_INTAn;
+        PCI_INTAn <= watch_PCI_INTAn and (not vio_async_out(0));
+
         trig0(31 downto 0) <= (
         0 => watch_PCI_INTAn,
         1 => R_FIFO_READn,
@@ -412,7 +424,8 @@ begin
         i_icon : icon
         port map
         (
-                control0 => control0
+                control0 => control0,
+                control1 => control1
         );
 
         i_ila : ila
@@ -423,4 +436,11 @@ begin
                 data => data,
                 trig0 => trig0
         );
+
+	i_vio : vio
+	port map
+	(
+		control => control1,
+		async_out => vio_async_out
+	);
 end SCHEMATIC;