X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/d452afd57d3469271a8532a9271ed7c14a53a427..696ded12bcd3df47aeefae2c685029a799d84abd:/dhwk/source/Verg_4.vhd

diff --git a/dhwk/source/Verg_4.vhd b/dhwk/source/Verg_4.vhd
index 6aafdad..e3900cf 100644
--- a/dhwk/source/Verg_4.vhd
+++ b/dhwk/source/Verg_4.vhd
@@ -1,32 +1,32 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_4.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity VERG_4 is
-	port
-	(
- 	IN_A		:in		std_logic_vector(3 downto 0);
- 	IN_B		:in		std_logic_vector(3 downto 0);
-	GLEICH	:out	std_logic
-	);
-end entity VERG_4 ;
-
-architecture VERG_4_DESIGN of VERG_4 is
-
-begin
-
-	process (IN_A,IN_B) 
-	begin 
-
-		if			IN_A	=	IN_B	then	GLEICH	<=	'1';
-			else											GLEICH	<=	'0';   
-		end if;
-
-	end process;
-
-end architecture VERG_4_DESIGN;
-
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+	port
+	(
+ 	IN_A		:in		std_logic_vector(3 downto 0);
+ 	IN_B		:in		std_logic_vector(3 downto 0);
+	GLEICH	:out	std_logic
+	);
+end entity VERG_4 ;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+	process (IN_A,IN_B) 
+	begin 
+
+		if			IN_A	=	IN_B	then	GLEICH	<=	'1';
+			else											GLEICH	<=	'0';   
+		end if;
+
+	end process;
+
+end architecture VERG_4_DESIGN;
+