X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/e00b64cc5780386174db7506cad5bccee09087b0..0d71737f8f2a2c3d4246600dbc0189890df7cbb9:/ethernet/ethernet.prj

diff --git a/ethernet/ethernet.prj b/ethernet/ethernet.prj
index 5bd7d4e..9086799 100644
--- a/ethernet/ethernet.prj
+++ b/ethernet/ethernet.prj
@@ -1,4 +1,3 @@
-vhdl work "source/top.vhd"
 verilog work "source/ethernet/eth_crc.v"
 verilog work "source/ethernet/eth_cop.v"
 verilog work "source/ethernet/eth_maccontrol.v"
@@ -26,3 +25,63 @@ verilog work "source/ethernet/eth_txstatem.v"
 verilog work "source/ethernet/eth_transmitcontrol.v"
 verilog work "source/ethernet/eth_macstatus.v"
 verilog work "source/ethernet/eth_clockgen.v"
+verilog work "source/pci/pci_target_unit.v"
+verilog work "source/pci/pci_target32_stop_crit.v"
+verilog work "source/pci/pci_delayed_sync.v"
+verilog work "source/pci/pci_wb_slave_unit.v"
+verilog work "source/pci/pci_frame_load_crit.v"
+verilog work "source/pci/pci_mas_ad_en_crit.v"
+verilog work "source/pci/pci_constants.v"
+verilog work "source/pci/pci_wbw_wbr_fifos.v"
+verilog work "source/pci/pci_wb_slave.v"
+verilog work "source/pci/pci_target32_trdy_crit.v"
+verilog work "source/pci/pci_target32_interface.v"
+verilog work "source/pci/pci_wbw_fifo_control.v"
+verilog work "source/pci/pci_wb_tpram.v"
+verilog work "source/pci/pci_par_crit.v"
+verilog work "source/pci/pci_conf_space.v"
+verilog work "source/pci/pci_target32_sm.v"
+verilog work "source/pci/pci_pciw_pcir_fifos.v"
+verilog work "source/pci/pci_serr_en_crit.v"
+verilog work "source/pci/pci_target32_devs_crit.v"
+verilog work "source/pci/pci_out_reg.v"
+verilog work "source/pci/pci_mas_ad_load_crit.v"
+verilog work "source/pci/pci_delayed_write_reg.v"
+verilog work "source/pci/pci_wbs_wbb3_2_wbb2.v"
+verilog work "source/pci/pci_wb_master.v"
+verilog work "source/pci/bus_commands.v"
+verilog work "source/pci/pci_rst_int.v"
+verilog work "source/pci/pci_sync_module.v"
+verilog work "source/pci/pci_master32_sm_if.v"
+verilog work "source/pci/pci_frame_crit.v"
+verilog work "source/pci/pci_user_constants.v"
+verilog work "source/pci/pci_io_mux_ad_load_crit.v"
+verilog work "source/pci/pci_pciw_fifo_control.v"
+verilog work "source/pci/pci_parity_check.v"
+verilog work "source/pci/pci_irdy_out_crit.v"
+verilog work "source/pci/pci_perr_crit.v"
+verilog work "source/pci/pci_mas_ch_state_crit.v"
+verilog work "source/pci/pci_spoci_ctrl.v"
+verilog work "source/pci/pci_wb_addr_mux.v"
+verilog work "source/pci/pci_perr_en_crit.v"
+verilog work "source/pci/pci_target32_clk_en.v"
+verilog work "source/pci/timescale.v"
+verilog work "source/pci/pci_serr_crit.v"
+verilog work "source/pci/pci_frame_en_crit.v"
+verilog work "source/pci/pci_master32_sm.v"
+verilog work "source/pci/pci_pci_tpram.v"
+verilog work "source/pci/pci_cur_out_reg.v"
+verilog work "source/pci/pci_io_mux.v"
+verilog work "source/pci/pci_wbr_fifo_control.v"
+verilog work "source/pci/pci_ram_16x40d.v"
+verilog work "source/pci/pci_io_mux_ad_en_crit.v"
+verilog work "source/pci/pci_async_reset_flop.v"
+verilog work "source/pci/pci_wb_decoder.v"
+verilog work "source/pci/pci_conf_cyc_addr_dec.v"
+verilog work "source/pci/pci_bridge32.v"
+verilog work "source/pci/pci_synchronizer_flop.v"
+verilog work "source/pci/pci_pcir_fifo_control.v"
+verilog work "source/pci/pci_cbe_en_crit.v"
+verilog work "source/pci/pci_pci_decoder.v"
+verilog work "source/pci/pci_in_reg.v"
+vhdl work "source/top.vhd"