X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/e672438961478e94cca88211c9c123defab280c4..078adaa6dde598b83d746458dd7140f567223e6a:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 4becb68..bf927d8 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(35 downto 0);
-   signal trig0      : std_logic_vector(7 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -209,7 +209,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );
    end component;
 
-component fifo_generator_v3_2
+component dhwk_fifo
         port (
         clk: IN std_logic;
         din: IN std_logic_VECTOR(7 downto 0);
@@ -236,8 +236,8 @@ end component;
     (
       control     : in    std_logic_vector(35 downto 0);
       clk         : in    std_logic;
-      data        : in    std_logic_vector(35 downto 0);
-      trig0       : in    std_logic_vector(7 downto 0)
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
     );
   end component;
 
@@ -250,9 +250,28 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
+	trig0(31 downto 0) <= (
+		0 => watch,
+		1 => R_FIFO_READn,
+		2 => R_FIFO_WRITEn,
+		3 => S_FIFO_READn,
+		4 => S_FIFO_WRITEn, 
+		16 => PCI_AD(0),
+		17 => PCI_AD(1),
+		18 => PCI_AD(2),
+		19 => PCI_AD(3),
+		20 => PCI_AD(4),
+		21 => PCI_AD(5),
+		22 => PCI_AD(6),
+		23 => PCI_AD(7),
+		27 => PCI_FRAMEn,
+		28 => PCI_CBEn(0),
+		29 => PCI_CBEn(1),
+		30 => PCI_CBEn(2),
+		31 => PCI_CBEn(3),
+		others => '0');
+
 	data(0) <= watch;
-	
 	data(1) <= R_EFn;
 	data(2) <= R_HFn;
 	data(3) <= R_FFn;
@@ -273,6 +292,9 @@ begin
 	data(18) <= SPC_RDY_OUT;
 	data(26 downto 19) <= S_FIFO_Q_OUT;
 	data(34 downto 27) <= R_FIFO_Q_OUT;
+	data(66 downto 35) <= PCI_AD(31 downto 0);
+	data(70 downto 67) <= PCI_CBEn(3 downto 0);
+	data(71) <= PCI_FRAMEn;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -342,7 +364,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
                  WRITE_XX7_6=>WRITE_XX7_6 );
 
-receive_fifo : fifo_generator_v3_2
+receive_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => R_FIFO_D_IN,
@@ -354,7 +376,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,
                         prog_full => R_HFn);
 
-send_fifo : fifo_generator_v3_2
+send_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => S_FIFO_D_IN,