X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/e672438961478e94cca88211c9c123defab280c4..2612d712ff5ef3f17a3d55ae22c71a1913fa1fee:/dhwk/source/fifo_control.vhd diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd index 1baa801..46ecd93 100644 --- a/dhwk/source/fifo_control.vhd +++ b/dhwk/source/fifo_control.vhd @@ -1,172 +1,171 @@ --- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007 - - - -LIBRARY ieee; - -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - - -entity FIFO_CONTROL is - Port ( FIFO_RDn : In std_logic; - FLAG_IN_0 : In std_logic; - FLAG_IN_4 : In std_logic; - HOLD : In std_logic; - KONST_1 : In std_logic; - PCI_CLOCK : In std_logic; - PSC_ENABLE : In std_logic; - R_EFn : In std_logic; - R_FFn : In std_logic; - R_HFn : In std_logic; - RESET : In std_logic; - S_EFn : In std_logic; - S_FFn : In std_logic; - S_FIFO_Q_OUT : In std_logic_vector (7 downto 0); - S_HFn : In std_logic; - SERIAL_IN : In std_logic; - SPC_ENABLE : In std_logic; - SPC_RDY_IN : In std_logic; - WRITE_XX1_0 : In std_logic; - R_ERROR : Out std_logic; - R_FIFO_D_IN : Out std_logic_vector (7 downto 0); - R_FIFO_READn : Out std_logic; - R_FIFO_RESETn : Out std_logic; - R_FIFO_RETRANSMITn : Out std_logic; - R_FIFO_WRITEn : Out std_logic; - RESERVE : Out std_logic; - S_ERROR : Out std_logic; - S_FIFO_READn : Out std_logic; - S_FIFO_RESETn : Out std_logic; - S_FIFO_RETRANSMITn : Out std_logic; - S_FIFO_WRITEn : Out std_logic; - SERIAL_OUT : Out std_logic; - SPC_RDY_OUT : Out std_logic; - SR_ERROR : Out std_logic; - SYNC_FLAG : Out std_logic_vector (7 downto 0)); -end FIFO_CONTROL; - -architecture SCHEMATIC of FIFO_CONTROL is - - SIGNAL gnd : std_logic := '0'; - SIGNAL vcc : std_logic := '1'; - - signal XXXR_FIFO_WRITEn : std_logic; - signal XXXS_FIFO_READn : std_logic; - signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0); - signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0); - - component SER_PAR_CON - Port ( PCI_CLOCK : In std_logic; - RESET : In std_logic; - SERIAL_IN : In std_logic; - SPC_ENABLE : In std_logic; - SYNC_R_FIFO_FFn : In std_logic; - PAR_OUT : Out std_logic_vector (7 downto 0); - R_FIFO_WRITEn : Out std_logic; - SPC_RDY_OUT : Out std_logic ); - end component; - - component PAR_SER_CON - Port ( PAR_IN : In std_logic_vector (7 downto 0); - PCI_CLOCK : In std_logic; - PSC_ENABLE : In std_logic; - RESET : In std_logic; - SPC_RDY_IN : In std_logic; - SYNC_S_FIFO_EFn : In std_logic; - S_FIFO_READn : Out std_logic; - SER_OUT : Out std_logic ); - end component; - - component FIFO_IO_CONTROL - Port ( FIFO_RDn : In std_logic; - PCI_CLOCK : In std_logic; - RESET : In std_logic; - SYNC_FLAG_1 : In std_logic; - SYNC_FLAG_7 : In std_logic; - WRITE_XX1_0 : In std_logic; - R_ERROR : Out std_logic; - R_FIFO_READn : Out std_logic; - R_FIFO_RESETn : Out std_logic; - R_FIFO_RETRANSMITn : Out std_logic; - S_ERROR : Out std_logic; - S_FIFO_RESETn : Out std_logic; - S_FIFO_RETRANSMITn : Out std_logic; - S_FIFO_WRITEn : Out std_logic; - SR_ERROR : Out std_logic ); - end component; - - component CONNECTING_FSM - Port ( PCI_CLOCK : In std_logic; - PSC_ENABLE : In std_logic; - RESET : In std_logic; - S_FIFO_Q_OUT : In std_logic_vector (7 downto 0); - SPC_ENABLE : In std_logic; - SYNC_R_FIFO_FFn : In std_logic; - SYNC_S_FIFO_EFn : In std_logic; - R_FIFO_D_IN : Out std_logic_vector (7 downto 0); - R_FIFO_WRITEn : Out std_logic; - S_FIFO_READn : Out std_logic ); - end component; - - component FLAG_BUS - Port ( FLAG_IN_0 : In std_logic; - FLAG_IN_4 : In std_logic; - HOLD : In std_logic; - KONS_1 : In std_logic; - PCI_CLOCK : In std_logic; - R_EFn : In std_logic; - R_FFn : In std_logic; - R_HFn : In std_logic; - S_EFn : In std_logic; - S_FFn : In std_logic; - S_HFn : In std_logic; - SYNC_FLAG : Out std_logic_vector (7 downto 0) ); - end component; - -begin - - SYNC_FLAG <= SYNC_FLAG_DUMMY; - - RESERVE <= gnd; - I23 : SER_PAR_CON - Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET, - SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE, - SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3), - PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0), - R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT ); - I22 : PAR_SER_CON - Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0), - PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE, - RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN, - SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5), - S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT ); - I21 : FIFO_IO_CONTROL - Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET, - SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1), - SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7), - WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR, - R_FIFO_READn=>R_FIFO_READn, - R_FIFO_RESETn=>R_FIFO_RESETn, - R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn, - S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn, - S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn, - S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR ); - I20 : CONNECTING_FSM - Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE, - RESET=>RESET, - S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0), - SPC_ENABLE=>SPC_ENABLE, - SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3), - SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5), - R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0), - R_FIFO_WRITEn=>XXXR_FIFO_WRITEn, - S_FIFO_READn=>XXXS_FIFO_READn ); - I19 : FLAG_BUS - Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD, - KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn, - R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn, - S_HFn=>S_HFn, - SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) ); - -end SCHEMATIC; +-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007 + + +LIBRARY ieee; + +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +entity FIFO_CONTROL is + Port ( FIFO_RDn : In std_logic; + FLAG_IN_0 : In std_logic; + FLAG_IN_4 : In std_logic; + HOLD : In std_logic; + KONST_1 : In std_logic; + PCI_CLOCK : In std_logic; + PSC_ENABLE : In std_logic; + R_EFn : In std_logic; + R_FFn : In std_logic; + R_HFn : In std_logic; + RESET : In std_logic; + S_EFn : In std_logic; + S_FFn : In std_logic; + S_FIFO_Q_OUT : In std_logic_vector (7 downto 0); + S_HFn : In std_logic; + SERIAL_IN : In std_logic; + SPC_ENABLE : In std_logic; + SPC_RDY_IN : In std_logic; + WRITE_XX1_0 : In std_logic; + R_ERROR : Out std_logic; + R_FIFO_D_IN : Out std_logic_vector (7 downto 0); + R_FIFO_READn : Out std_logic; + R_FIFO_RESETn : Out std_logic; + R_FIFO_RETRANSMITn : Out std_logic; + R_FIFO_WRITEn : Out std_logic; + RESERVE : Out std_logic; + S_ERROR : Out std_logic; + S_FIFO_READn : Out std_logic; + S_FIFO_RESETn : Out std_logic; + S_FIFO_RETRANSMITn : Out std_logic; + S_FIFO_WRITEn : Out std_logic; + SERIAL_OUT : Out std_logic; + SPC_RDY_OUT : Out std_logic; + SR_ERROR : Out std_logic; + SYNC_FLAG : Out std_logic_vector (7 downto 0)); +end FIFO_CONTROL; + +architecture SCHEMATIC of FIFO_CONTROL is + + SIGNAL gnd : std_logic := '0'; + SIGNAL vcc : std_logic := '1'; + + signal XXXR_FIFO_WRITEn : std_logic; + signal XXXS_FIFO_READn : std_logic; + signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0); + signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0); + + component SER_PAR_CON + Port ( PCI_CLOCK : In std_logic; + RESET : In std_logic; + SERIAL_IN : In std_logic; + SPC_ENABLE : In std_logic; + SYNC_R_FIFO_FFn : In std_logic; + PAR_OUT : Out std_logic_vector (7 downto 0); + R_FIFO_WRITEn : Out std_logic; + SPC_RDY_OUT : Out std_logic ); + end component; + + component PAR_SER_CON + Port ( PAR_IN : In std_logic_vector (7 downto 0); + PCI_CLOCK : In std_logic; + PSC_ENABLE : In std_logic; + RESET : In std_logic; + SPC_RDY_IN : In std_logic; + SYNC_S_FIFO_EFn : In std_logic; + S_FIFO_READn : Out std_logic; + SER_OUT : Out std_logic ); + end component; + + component FIFO_IO_CONTROL + Port ( FIFO_RDn : In std_logic; + PCI_CLOCK : In std_logic; + RESET : In std_logic; + SYNC_FLAG_1 : In std_logic; + SYNC_FLAG_7 : In std_logic; + WRITE_XX1_0 : In std_logic; + R_ERROR : Out std_logic; + R_FIFO_READn : Out std_logic; + R_FIFO_RESETn : Out std_logic; + R_FIFO_RETRANSMITn : Out std_logic; + S_ERROR : Out std_logic; + S_FIFO_RESETn : Out std_logic; + S_FIFO_RETRANSMITn : Out std_logic; + S_FIFO_WRITEn : Out std_logic; + SR_ERROR : Out std_logic ); + end component; + + component CONNECTING_FSM + Port ( PCI_CLOCK : In std_logic; + PSC_ENABLE : In std_logic; + RESET : In std_logic; + S_FIFO_Q_OUT : In std_logic_vector (7 downto 0); + SPC_ENABLE : In std_logic; + SYNC_R_FIFO_FFn : In std_logic; + SYNC_S_FIFO_EFn : In std_logic; + R_FIFO_D_IN : Out std_logic_vector (7 downto 0); + R_FIFO_WRITEn : Out std_logic; + S_FIFO_READn : Out std_logic ); + end component; + + component FLAG_BUS + Port ( FLAG_IN_0 : In std_logic; + FLAG_IN_4 : In std_logic; + HOLD : In std_logic; + KONS_1 : In std_logic; + PCI_CLOCK : In std_logic; + R_EFn : In std_logic; + R_FFn : In std_logic; + R_HFn : In std_logic; + S_EFn : In std_logic; + S_FFn : In std_logic; + S_HFn : In std_logic; + SYNC_FLAG : Out std_logic_vector (7 downto 0) ); + end component; + +begin + + SYNC_FLAG <= SYNC_FLAG_DUMMY; + + RESERVE <= gnd; + I23 : SER_PAR_CON + Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET, + SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE, + SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3), + PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0), + R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT ); + I22 : PAR_SER_CON + Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0), + PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE, + RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN, + SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5), + S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT ); + I21 : FIFO_IO_CONTROL + Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET, + SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1), + SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7), + WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR, + R_FIFO_READn=>R_FIFO_READn, + R_FIFO_RESETn=>R_FIFO_RESETn, + R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn, + S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn, + S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn, + S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR ); + I20 : CONNECTING_FSM + Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE, + RESET=>RESET, + S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0), + SPC_ENABLE=>SPC_ENABLE, + SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3), + SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5), + R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0), + R_FIFO_WRITEn=>XXXR_FIFO_WRITEn, + S_FIFO_READn=>XXXS_FIFO_READn ); + I19 : FLAG_BUS + Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD, + KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn, + R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn, + S_HFn=>S_HFn, + SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) ); + +end SCHEMATIC;