X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/ee14ffda64ebaf81e7bed329b9db70012d5ffbde..f026519d99c0b3afb0560431530bb0a5b11e705b:/dhwk_old/source/generic_dpram.v diff --git a/dhwk_old/source/generic_dpram.v b/dhwk_old/source/generic_dpram.v index 816122e..e75a91e 100644 --- a/dhwk_old/source/generic_dpram.v +++ b/dhwk_old/source/generic_dpram.v @@ -66,7 +66,10 @@ // CVS Revision History // // $Log: generic_dpram.v,v $ -// Revision 1.2 2007-02-11 22:15:39 sithglan +// Revision 1.3 2007-02-11 22:18:24 michael +// component for dram +// +// Revision 1.2 2007/02/11 22:15:39 sithglan // define xilinix and fpga // // Revision 1.1 2007/02/11 22:05:26 sithglan @@ -118,8 +121,8 @@ module generic_dpram( // // Default address and data buses width // - parameter aw = 5; // number of bits in address-bus - parameter dw = 16; // number of bits in data-bus + parameter aw = 12; // number of bits in address-bus + parameter dw = 8; // number of bits in data-bus // // Generic synchronous double-port RAM interface