X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/f7be01477b0e068cbd8bc736401baff92def833b..1eb920cafb45866e18e34e319ae747af9753665d:/heartbeat/source/heartbeat.vhd

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index e079bbb..03180ef 100644
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -5,7 +5,7 @@ use ieee.std_logic_unsigned.all;
 
 entity heartbeat is
 generic (
-	divider : std_logic_vector(31 downto 0) := X"01F78A40"
+	divider : std_logic_vector(31 downto 0) := "00000000001111101111000101001000"
 );
 
 port (
@@ -14,7 +14,11 @@ port (
 	led2_o : out std_logic;
 	led3_o : out std_logic;
 	led4_o : out std_logic;
-	led5_o : out std_logic
+	led5_o : out std_logic;
+	led6_o : out std_logic;
+	led7_o : out std_logic;
+	led8_o : out std_logic;
+	led9_o : out std_logic
 );   
 
 end heartbeat;
@@ -23,24 +27,43 @@ architecture rtl of heartbeat is
 begin
 
 process(clk_i, nrst_i)
-variable counter : std_logic_vector(31 downto 0);
-variable state : std_logic := '0';
+variable counter : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
+variable state : std_logic_vector(7 downto 0) := "00000001";
+variable direction : std_logic := '0';
 begin
 
-if (clk_i'event AND clk_i = '1') then
-	if nrst_i = '0' then
-		counter := (others => '0');
-        else
-		led5_o <= state;
-		led2_o <= state;
-		led4_o <= not state;
-		led3_o <= not state;
+if (rising_edge(clk_i)) then
+--	if nrst_i = '0' then
+--		counter := (others => '0');
+--        else
+		led2_o <= state(0);
+		led3_o <= state(1);
+		led4_o <= state(2);
+		led5_o <= state(3);
+		led6_o <= state(4);
+		led7_o <= state(5);
+		led8_o <= state(6);
+		led9_o <= state(7);
 		counter := counter + 1;
 		if counter = divider then
-			state := not state;
+			if state(3) = '1' then
+				direction := '1';
+			end if;
+
+			if state(0) = '1' then
+				direction := '0';
+			end if;
+
+			if direction = '0' then
+				state(7 downto 1) := state(6 downto 0);
+				state(0) := '0';
+			else
+				state(6 downto 0) := state(7 downto 1);
+				state(7) := '0';
+			end if;
 			counter := (others => '0');
 	        end if;
-	end if;
+--	end if;
 end if;
 end process;
 end architecture;