X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/f822acebac284df723c5196d47295f447c5338df..e672438961478e94cca88211c9c123defab280c4:/dhwk/source/fifo_control.vhd

diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 9a93404..1baa801 100644
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -43,9 +43,7 @@ entity FIFO_CONTROL is
              SERIAL_OUT : Out   std_logic;
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0);
-	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
-	     SER_PAR_OUT : Out std_logic_vector (7 downto 0));
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0));
 end FIFO_CONTROL;
 
 architecture SCHEMATIC of FIFO_CONTROL is
@@ -57,7 +55,6 @@ architecture SCHEMATIC of FIFO_CONTROL is
    signal XXXS_FIFO_READn : std_logic;
    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
-   signal watcher : std_logic_vector (7 downto 0);
 
    component SER_PAR_CON
       Port ( PCI_CLOCK : In    std_logic;
@@ -130,16 +127,13 @@ architecture SCHEMATIC of FIFO_CONTROL is
 begin
 
    SYNC_FLAG <= SYNC_FLAG_DUMMY;
-   PAR_SER_IN <= S_FIFO_Q_OUT;
-   SER_PAR_OUT <= watcher;
-   R_FIFO_D_IN(7 downto 0) <= watcher;
 
    RESERVE <= gnd;
    I23 : SER_PAR_CON
       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
-                 PAR_OUT(7 downto 0)=>watcher,
+                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
    I22 : PAR_SER_CON
       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),