old 7seg thingie

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 0e03a31b223e9ce5216ccf579b7f4b54d38b50fe..accd1a382677ce6d91bcf022783c6b4c6f212d41 100644 (file)
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -109,6 +109,27 @@ port (
 );\r
 end component;\r
 \r
 );\r
 end component;\r
 \r

+component wb_7seg_new\r
+port (\r
+       clk_i           : in std_logic;\r
+       nrst_i          : in std_logic;\r
+       \r
+       wb_adr_i        : in std_logic_vector(24 downto 1);\r
+       wb_dat_o        : out std_logic_vector(15 downto 0);\r
+       wb_dat_i        : in std_logic_vector(15 downto 0);\r
+       wb_sel_i        : in std_logic_vector(1 downto 0);\r
+       wb_we_i         : in std_logic;\r
+       wb_stb_i        : in std_logic;\r
+       wb_cyc_i        : in std_logic;\r
+       wb_ack_o        : out std_logic;\r
+       wb_err_o        : out std_logic;\r
+       wb_int_o        : out std_logic;\r
+       \r
+       DISP_SEL        : inout std_logic_vector(3 downto 0);\r
+       DISP_LED        : out std_logic_vector(6 downto 0)\r
+);\r
+end component;\r
+\r

 signal         wb_adr :                std_logic_vector(24 downto 1);   \r
 signal wb_dat_out :    std_logic_vector(15 downto 0);\r
 signal         wb_dat_in :             std_logic_vector(15 downto 0);\r
 signal         wb_adr :                std_logic_vector(24 downto 1);   \r
 signal wb_dat_out :    std_logic_vector(15 downto 0);\r
 signal         wb_dat_in :             std_logic_vector(15 downto 0);\r