From: michael Date: Sat, 10 Mar 2007 23:24:03 +0000 (+0000) Subject: add PCI_nREQ X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/055a9fc3314c4d925d5095295b577df130dc7f64?hp=f80858bad8da614b4a8d0acf454895f627aaa9ec add PCI_nREQ --- diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf index 57b59c4..1924315 100644 --- a/heartbeat/raggedstone.ucf +++ b/heartbeat/raggedstone.ucf @@ -48,6 +48,7 @@ NET "PCI_nSERR" LOC = "B12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; NET "PCI_nSTOP" LOC = "A12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; NET "PCI_nTRDY" LOC = "B13" | IOSTANDARD = PCI33_3 | SLEW = FAST ; NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "PCI_nREQ" LOC = "C18" | IOSTANDARD = PCI33_3 ; NET "LED5" LOC = "AB4" | IOSTANDARD = LVCMOS33 ; NET "LED4" LOC = "AA4" | IOSTANDARD = LVCMOS33 ; NET "IDE1" LOC = "Y1" | IOSTANDARD = LVCMOS33 ; diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd index c798294..3d369cf 100644 --- a/heartbeat/source/top_raggedstone.vhd +++ b/heartbeat/source/top_raggedstone.vhd @@ -44,6 +44,7 @@ port ( -- General PCI_CLK : in std_logic; PCI_nRES : in std_logic; + PCI_nREQ : out std_logic; -- PCI target 32bits PCI_AD : inout std_logic_vector(31 downto 0); @@ -161,6 +162,8 @@ end component; begin + PCI_nREQ <= '1'; + --+-----------------------------------------+ --| PCI Target | --+-----------------------------------------+