From: michael <michael>
Date: Sat, 10 Mar 2007 21:35:08 +0000 (+0000)
Subject: rename fifo to dhwk_fifo
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/078adaa6dde598b83d746458dd7140f567223e6a?ds=inline;hp=08ef7f18c4131c6a5a61948a3a5543c6d9cb89b0

rename fifo to dhwk_fifo
---

diff --git a/dhwk/Makefile b/dhwk/Makefile
index 875f05a..dfb7422 100644
--- a/dhwk/Makefile
+++ b/dhwk/Makefile
@@ -11,7 +11,8 @@ icon.edn: icon.arg
 ila.edn: ila.arg
 	$(CHIPSCOPE)/bin/lin/generate.sh ila -f=$<
 
-fifo_generator_v3_2.ngc: fifo.xco
+dhwk_fifo.ngc: fifo.xco
 	coregen -b $<
+	-rmdir -p tmp
 
 include ../common/Makefile.common
diff --git a/dhwk/fifo.xco b/dhwk/fifo.xco
index 22c49f3..9b54e67 100644
--- a/dhwk/fifo.xco
+++ b/dhwk/fifo.xco
@@ -23,7 +23,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 3.2
 # BEGIN Parameters
 CSET almost_empty_flag=true
 CSET almost_full_flag=true
-CSET component_name=fifo_generator_v3_2
+CSET component_name=dhwk_fifo
 CSET data_count=false
 CSET data_count_width=12
 CSET dout_reset_value=0
diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 84f04dd..bf927d8 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -209,7 +209,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );
    end component;
 
-component fifo_generator_v3_2
+component dhwk_fifo
         port (
         clk: IN std_logic;
         din: IN std_logic_VECTOR(7 downto 0);
@@ -364,7 +364,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
                  WRITE_XX7_6=>WRITE_XX7_6 );
 
-receive_fifo : fifo_generator_v3_2
+receive_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => R_FIFO_D_IN,
@@ -376,7 +376,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,
                         prog_full => R_HFn);
 
-send_fifo : fifo_generator_v3_2
+send_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => S_FIFO_D_IN,