From: sithglan Date: Sun, 11 Mar 2007 08:47:55 +0000 (+0000) Subject: move config space header into pci core directory X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1 move config space header into pci core directory --- diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj index 05666d3..056bf47 100644 --- a/dhwk/dhwk.prj +++ b/dhwk/dhwk.prj @@ -1,14 +1,15 @@ vhdl work "source/verg_8.vhd" vhdl work "source/synplify.vhd" vhdl work "source/parity_out.vhd" -vhdl work "source/config_wr_0.vhd" -vhdl work "source/config_rd_0.vhd" -vhdl work "source/config_mux_0.vhd" -vhdl work "source/config_3Ch.vhd" -vhdl work "source/config_10h.vhd" -vhdl work "source/config_08h.vhd" -vhdl work "source/config_04h.vhd" -vhdl work "source/config_00h.vhd" +vhdl work "source/pci/config_space_header.vhd" +vhdl work "source/pci/config_wr_0.vhd" +vhdl work "source/pci/config_rd_0.vhd" +vhdl work "source/pci/config_mux_0.vhd" +vhdl work "source/pci/config_3Ch.vhd" +vhdl work "source/pci/config_10h.vhd" +vhdl work "source/pci/config_08h.vhd" +vhdl work "source/pci/config_04h.vhd" +vhdl work "source/pci/config_00h.vhd" vhdl work "source/Verg_4.vhd" vhdl work "source/Verg_2.vhd" vhdl work "source/REG.vhd" @@ -23,7 +24,6 @@ vhdl work "source/steuerung.vhd" vhdl work "source/reg_io.vhd" vhdl work "source/parity.vhd" vhdl work "source/io_mux_reg.vhd" -vhdl work "source/config_space_header.vhd" vhdl work "source/IO_RW_SEL.vhd" vhdl work "source/DATA_MUX.vhd" vhdl work "source/user_io.vhd" diff --git a/dhwk/source/config_00h.vhd b/dhwk/source/config_00h.vhd deleted file mode 100644 index 98b4532..0000000 --- a/dhwk/source/config_00h.vhd +++ /dev/null @@ -1,28 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_00H.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_00H is - port - ( - VENDOR_ID :in std_logic_vector (15 downto 0); - CONF_DATA_00H :out std_logic_vector (31 downto 0) - ); -end entity CONFIG_00H; - -architecture CONFIG_00H_DESIGN of CONFIG_00H is - - -- PCI Configuration Space Header Addr : HEX 00 -- - - constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--???? - --constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--???? - -begin - - CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; - -end architecture CONFIG_00H_DESIGN; diff --git a/dhwk/source/config_04h.vhd b/dhwk/source/config_04h.vhd deleted file mode 100644 index 70d0c9f..0000000 --- a/dhwk/source/config_04h.vhd +++ /dev/null @@ -1,113 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_04H.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_04H is - port - ( - PCI_CLOCK :in std_logic; - PCI_RSTn :in std_logic; - SERR :in std_logic; - PERR :in std_logic; - AD_REG :in std_logic_vector(31 downto 0); - CBE_REGn :in std_logic_vector( 3 downto 0); - CONF_WR_04H :in std_logic; - CONF_DATA_04H :out std_logic_vector(31 downto 0) - ); -end entity CONFIG_04H; - -architecture CONFIG_04H_DESIGN of CONFIG_04H is - - signal CONF_STATUS :std_logic_vector(31 downto 16); - signal CONF_COMMAND :std_logic_vector(15 downto 0); - -begin - - --******************************************************************* - --************* PCI Configuration Space Header "STATUS" ************* - --******************************************************************* - - CONF_STATUS(20 downto 16) <= "00000";-- Reserved - CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz - CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O" - CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back - CONF_STATUS(24 ) <= '0';-- Master : - --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL" - CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL" - --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL" - --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved - CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort - CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort - CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort - --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR - --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR - - process (PCI_CLOCK,PCI_RSTn) - begin - if PCI_RSTn = '0' then - CONF_STATUS(30) <= '0'; - CONF_STATUS(31) <= '0'; - - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then - if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then - CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); - CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); - - else - CONF_STATUS(30) <= SERR or CONF_STATUS(30); - CONF_STATUS(31) <= PERR or CONF_STATUS(31); - - end if; - end if; -end process; - - --******************************************************************* - --*********** PCI Configuration Space Header "COMMAND" ************** - --******************************************************************* - --- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ??? --- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ??? --- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus --- CONF_COMMAND( 3) <= '0';-- Special Cycle ??? --- CONF_COMMAND( 4) <= '0';-- Master ??? --- CONF_COMMAND( 5) <= '0';-- VGA ??? --- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable -CONF_COMMAND( 7) <= '0';-- address/data stepping ??? --- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn" --- CONF_COMMAND( 9) <= '0';-- fast back-to-back --- CONF_COMMAND(10) <= '0';-- Reserved --- CONF_COMMAND(11) <= '0';-- Reserved --- CONF_COMMAND(12) <= '0';-- Reserved --- CONF_COMMAND(13) <= '0';-- Reserved --- CONF_COMMAND(14) <= '0';-- Reserved --- CONF_COMMAND(15) <= '0';-- Reserved - -process (PCI_CLOCK,PCI_RSTn) -begin - if PCI_RSTn = '0' then - CONF_COMMAND(15 downto 8) <= (others =>'0'); - CONF_COMMAND( 6 downto 0) <= (others =>'0'); - - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then - - if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then - CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); - else - CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8); - end if; - - if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then - CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0); - else - CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0); - end if; - end if; -end process; - -CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; - -end architecture CONFIG_04H_DESIGN; diff --git a/dhwk/source/config_08h.vhd b/dhwk/source/config_08h.vhd deleted file mode 100644 index 7b19df6..0000000 --- a/dhwk/source/config_08h.vhd +++ /dev/null @@ -1,28 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_08H.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_08H is - port - ( - REVISION_ID :in std_logic_vector ( 7 downto 0); - CONF_DATA_08H :out std_logic_vector (31 downto 0) - ); -end entity CONFIG_08H; - -architecture CONFIG_08H_DESIGN of CONFIG_08H is - - -- PCI Configuration Space Header Addr : HEX 08 -- - - constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";--other comm. device - --constant CONF_REVISION_ID :std_logic_vector ( 7 downto 0) := X"00"; - -begin - - CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; - -end architecture CONFIG_08H_DESIGN; diff --git a/dhwk/source/config_10h.vhd b/dhwk/source/config_10h.vhd deleted file mode 100644 index ad55b17..0000000 --- a/dhwk/source/config_10h.vhd +++ /dev/null @@ -1,77 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_10H.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_10H is - port - ( - PCI_CLOCK :in std_logic; - PCI_RSTn :in std_logic; - AD_REG :in std_logic_vector(31 downto 0); - CBE_REGn :in std_logic_vector( 3 downto 0); - CONF_WR_10H :in std_logic; - CONF_DATA_10H :out std_logic_vector(31 downto 0) - ); -end entity CONFIG_10H; - -architecture CONFIG_10H_DESIGN of CONFIG_10H is - - signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0); - -begin - - --******************************************************************* - --***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ****** - --******************************************************************* - - CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O" - CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE - - process (PCI_CLOCK,PCI_RSTn) - begin - - -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0'); - if PCI_RSTn = '0' then - CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0'); - - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then - - if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then - CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24); - else - CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24); - end if; - - if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then - CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16); - else - CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16); - end if; - - if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then - CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8); - else - CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8); - end if; - - -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then - -- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2); - -- else - -- CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2); - -- end if; - - if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then - CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4); - else - CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4); - end if; - end if; -end process; - -CONF_DATA_10H <= CONF_BAS_ADDR_REG; - -end architecture CONFIG_10H_DESIGN; diff --git a/dhwk/source/config_3Ch.vhd b/dhwk/source/config_3Ch.vhd deleted file mode 100644 index 2c79f4f..0000000 --- a/dhwk/source/config_3Ch.vhd +++ /dev/null @@ -1,59 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_3CH.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_3CH is - port ( - PCI_CLOCK :in std_logic; - PCI_RSTn :in std_logic; - AD_REG :in std_logic_vector (31 downto 0); - CBE_REGn :in std_logic_vector ( 3 downto 0); - CONF_WR_3CH :in std_logic; - CONF_DATA_3CH :out std_logic_vector (31 downto 0) - ); -end entity CONFIG_3CH; - -architecture CONFIG_3CH_DESIGN of CONFIG_3CH is - - -- PCI Configuration Space Header Addr : HEX 3C -- - - signal CONF_MAX_LAT :std_logic_vector (31 downto 24); - signal CONF_MIN_GNT :std_logic_vector (23 downto 16); - signal CONF_INT_PIN :std_logic_vector (15 downto 8); - signal CONF_INT_LINE :std_logic_vector ( 7 downto 0); - - constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011"; -begin - - --******************************************************************* - --*********** PCI Configuration Space Header "INTERRUPT" ************ - --******************************************************************* - - CONF_MAX_LAT <= X"00"; - CONF_MIN_GNT <= X"00"; - -- CONF_INT_PIN <= X"00"; -- Interrupt - - CONF_INT_PIN <= X"01"; -- Interrupt A - -- CONF_INT_PIN <= X"02"; -- Interrupt B - -- CONF_INT_PIN <= X"03"; -- Interrupt C - -- CONF_INT_PIN <= X"04"; -- Interrupt D - -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert - - process (PCI_CLOCK,PCI_RSTn) - begin - if PCI_RSTn = '0' then - CONF_INT_LINE <= (others => '0'); - - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then - if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then - CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0); - end if; - end if; - end process; - - CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE; - -end architecture CONFIG_3CH_DESIGN; diff --git a/dhwk/source/config_mux_0.vhd b/dhwk/source/config_mux_0.vhd deleted file mode 100644 index f1b34f7..0000000 --- a/dhwk/source/config_mux_0.vhd +++ /dev/null @@ -1,43 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_MUX_0.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_MUX_0 is - port - ( - READ_SEL :in std_logic_vector( 2 downto 0); - CONF_DATA_00H :in std_logic_vector(31 downto 0); - CONF_DATA_04H :in std_logic_vector(31 downto 0); - CONF_DATA_08H :in std_logic_vector(31 downto 0); - CONF_DATA_10H :in std_logic_vector(31 downto 0); - CONF_DATA_3CH :in std_logic_vector(31 downto 0); - --CONF_DATA_40H :in std_logic_vector(31 downto 0); - CONF_DATA :out std_logic_vector(31 downto 0) - ); -end entity CONFIG_MUX_0; - -architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is - - signal MUX :std_logic_vector (31 downto 0); - -begin - - --******************************************************************* - --******************* PCI Read Config-MUX ************************** - --******************************************************************* - - MUX <= CONF_DATA_00H when READ_SEL <= "000" else - CONF_DATA_04H when READ_SEL <= "001" else - CONF_DATA_08H when READ_SEL <= "010" else - CONF_DATA_10H when READ_SEL <= "011" else - CONF_DATA_3CH when READ_SEL <= "100" else - -- CONF_DATA_40H when READ_SEL <= "101" else - X"00000000"; - - CONF_DATA <= MUX; - -end architecture CONFIG_MUX_0_DESIGN; diff --git a/dhwk/source/config_rd_0.vhd b/dhwk/source/config_rd_0.vhd deleted file mode 100644 index 92b6a98..0000000 --- a/dhwk/source/config_rd_0.vhd +++ /dev/null @@ -1,134 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_RD_0.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_RD_0 is - port - ( - ADDR_REG :in std_logic_vector (31 downto 0); - CF_RD_COM :in std_logic; - READ_SEL :out std_logic_vector ( 2 downto 0) - ); -end entity CONFIG_RD_0; - -architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is - - -- - -- - -- - -- - -- - -- PCI Configuration Space Header - -- - -- \ Bit - -- \ - --Address |31 24|23 16|15 8|7 0| - ----------------------------------------------------------------- - --00 |Device ID |Vendor ID | - --04 |Status |Command | - --08 |Class Code |Revision ID| - --0C |BIST |Header Type|Latency T. |Cache L.S. | - --10-24 |Base Address Register | - --28 |Cardbus CIS Pointer | - --2C |Subsystem ID |Subsystem Vendor ID | - --30 |Expansion ROM Base Address | - --34 |Reserved | - --38 |Reserved | - --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line | - --40-FF | | - ----------------------------------------------------------------- - - - --PCI Bus Commands - --C/BE[3..0] Command Type - -------------------------------------- - -- 0000 Interrupt Acknowledge - -- 0001 Special Cycle - -- 0010 I/O Read - -- 0011 I/O Write - -- 0100 Reserved - -- 0101 Reserved - -- 0110 Memory Read - -- 0111 Memory Write - -- - -- 1000 Reserved - -- 1001 Reserved - -- 1010 Configuration Read - -- 1011 Configuration Write - -- 1100 Memory Read Multiple - -- 1101 Dual Address Cycle - -- 1110 Memory Read Line - -- 1111 Memory Write and Invalidate - - - --PCI Byte Enable - --C/BE[3..0] gueltige Datenbits - ------------------------------- - -- 0000 AD 31..0 - -- 1000 AD 23..0 - -- 1100 AD 15..0 - -- 1110 AD 7..0 - - constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000"; - constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001"; - constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010"; - constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011"; - constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100"; - constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101"; - constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110"; - constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111"; - constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000"; - constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001"; - constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010"; - constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011"; - constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100"; - constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101"; - constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110"; - constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111"; - - signal MUX :std_logic_vector(31 downto 0); - signal CONFIG_ADDR :std_logic_vector( 7 downto 0); - -begin - - CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0); - - --******************************************************************* - --*********************** PCI Read Address ************************** - --******************************************************************* - - process (CF_RD_COM, CONFIG_ADDR) - begin - - if CF_RD_COM = '1' then - if CONFIG_ADDR = X"00" then - READ_SEL <= "000"; - - elsif CONFIG_ADDR = X"04" then - READ_SEL <= "001"; - - elsif CONFIG_ADDR = X"08" then - READ_SEL <= "010"; - - elsif CONFIG_ADDR = X"10" then - READ_SEL <= "011"; - - elsif CONFIG_ADDR = X"3C" then - READ_SEL <= "100"; - - elsif CONFIG_ADDR = X"40" then - READ_SEL <= "101"; - - else - READ_SEL <= "111"; - end if; - else - READ_SEL <= "111"; - end if; - end process; - -end architecture CONFIG_RD_0_DESIGN; diff --git a/dhwk/source/config_space_header.vhd b/dhwk/source/config_space_header.vhd deleted file mode 100644 index 15db761..0000000 --- a/dhwk/source/config_space_header.vhd +++ /dev/null @@ -1,155 +0,0 @@ --- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007 - -LIBRARY ieee; - -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - - -entity CONFIG_SPACE_HEADER is - Port ( AD_REG : In std_logic_vector (31 downto 0); - ADDR_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - CF_RD_COM : In std_logic; - CF_WR_COM : In std_logic; - IRDY_REGn : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - PERR : In std_logic; - REVISION_ID : In std_logic_vector (7 downto 0); - SERR : In std_logic; - TRDYn : In std_logic; - VENDOR_ID : In std_logic_vector (15 downto 0); - CONF_DATA : Out std_logic_vector (31 downto 0); - CONF_DATA_04H : Out std_logic_vector (31 downto 0); - CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); -end CONFIG_SPACE_HEADER; - -architecture SCHEMATIC of CONFIG_SPACE_HEADER is - - SIGNAL gnd : std_logic := '0'; - SIGNAL vcc : std_logic := '1'; - - signal CONF_WR_04H : std_logic; - signal CONF_WR_10H : std_logic; - signal CONF_WR_3CH : std_logic; - signal CONF_READ_SEL : std_logic_vector (2 downto 0); - signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0); - signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0); - signal CONF_DATA_3CH : std_logic_vector (31 downto 0); - signal CONF_DATA_08H : std_logic_vector (31 downto 0); - signal CONF_DATA_00H : std_logic_vector (31 downto 0); - - component CONFIG_MUX_0 - Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0); - CONF_DATA_04H : In std_logic_vector (31 downto 0); - CONF_DATA_08H : In std_logic_vector (31 downto 0); - CONF_DATA_10H : In std_logic_vector (31 downto 0); - CONF_DATA_3CH : In std_logic_vector (31 downto 0); - READ_SEL : In std_logic_vector (2 downto 0); - CONF_DATA : Out std_logic_vector (31 downto 0) ); - end component; - - component CONFIG_RD_0 - Port ( ADDR_REG : In std_logic_vector (31 downto 0); - CF_RD_COM : In std_logic; - READ_SEL : Out std_logic_vector (2 downto 0) ); - end component; - - component CONFIG_WR_0 - Port ( ADDR_REG : In std_logic_vector (31 downto 0); - CF_WR_COM : In std_logic; - IRDY_REGn : In std_logic; - TRDYn : In std_logic; - CONF_WR_04H : Out std_logic; - CONF_WR_10H : Out std_logic; - CONF_WR_3CH : Out std_logic ); - end component; - - component CONFIG_3CH - Port ( AD_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - CONF_WR_3CH : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - CONF_DATA_3CH : Out std_logic_vector (31 downto 0) ); - end component; - - component CONFIG_10H - Port ( AD_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - CONF_WR_10H : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); - end component; - - component CONFIG_08H - Port ( REVISION_ID : In std_logic_vector (7 downto 0); - CONF_DATA_08H : Out std_logic_vector (31 downto 0) ); - end component; - - component CONFIG_00H - Port ( VENDOR_ID : In std_logic_vector (15 downto 0); - CONF_DATA_00H : Out std_logic_vector (31 downto 0) ); - end component; - - component CONFIG_04H - Port ( AD_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - CONF_WR_04H : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - PERR : In std_logic; - SERR : In std_logic; - CONF_DATA_04H : Out std_logic_vector (31 downto 0) ); - end component; - -begin - - CONF_DATA_04H <= CONF_DATA_04H_DUMMY; - CONF_DATA_10H <= CONF_DATA_10H_DUMMY; - - I10 : CONFIG_MUX_0 - Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0), - CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0), - CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0), - CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0), - CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0), - READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0), - CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) ); - I9 : CONFIG_RD_0 - Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), - CF_RD_COM=>CF_RD_COM, - READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) ); - I8 : CONFIG_WR_0 - Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), - CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn, - TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H, - CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH ); - I6 : CONFIG_3CH - Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), - CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK, - PCI_RSTn=>PCI_RSTn, - CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) ); - I5 : CONFIG_10H - Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), - CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK, - PCI_RSTn=>PCI_RSTn, - CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) ); - I4 : CONFIG_08H - Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0), - CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) ); - I3 : CONFIG_00H - Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0), - CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) ); - I2 : CONFIG_04H - Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), - CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK, - PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR, - CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) ); - -end SCHEMATIC; diff --git a/dhwk/source/config_wr_0.vhd b/dhwk/source/config_wr_0.vhd deleted file mode 100644 index 9e1e2dc..0000000 --- a/dhwk/source/config_wr_0.vhd +++ /dev/null @@ -1,140 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_WR_0.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_WR_0 is - port - ( - ADDR_REG :in std_logic_vector(31 downto 0); - CF_WR_COM :in std_logic; - IRDY_REGn :in std_logic; - TRDYn :in std_logic; - CONF_WR_04H :out std_logic; - CONF_WR_10H :out std_logic; - CONF_WR_3CH :out std_logic - --CONF_WR_40H :out std_logic - ); -end entity CONFIG_WR_0; - -architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is - - -- - -- - -- - -- - -- - -- PCI Configuration Space Header - -- - -- \ Bit - -- \ - --Address |31 24|23 16|15 8|7 0| - ----------------------------------------------------------------- - --00 |Device ID |Vendor ID | - --04 |Status |Command | - --08 |Class Code |Revision ID | - --0C |BIST |Header Type |Latency T. |Cache L.S. | - --10-24 |Base Address Register | - --28 |Cardbus CIS Pointer | - --2C |Subsystem ID |Subsystem Vendor ID | - --30 |Expansion ROM Base Address | - --34 |Reserved | - --38 |Reserved | - --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line | - --40-FF | | - ----------------------------------------------------------------- - - - --PCI Bus Commands - --C/BE[3..0] Command Type - -------------------------------------- - -- 0000 Interrupt Acknowledge - -- 0001 Special Cycle - -- 0010 I/O Read - -- 0011 I/O Write - -- 0100 Reserved - -- 0101 Reserved - -- 0110 Memory Read - -- 0111 Memory Write - -- - -- 1000 Reserved - -- 1001 Reserved - -- 1010 Configuration Read - -- 1011 Configuration Write - -- 1100 Memory Read Multiple - -- 1101 Dual Address Cycle - -- 1110 Memory Read Line - -- 1111 Memory Write and Invalidate - - - --PCI Byte Enable - --C/BE[3..0] gueltige Datenbits - ------------------------------- - -- 0000 AD 31..0 - -- 1000 AD 23..0 - -- 1100 AD 15..0 - -- 1110 AD 7..0 - - constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000"; - constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001"; - constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010"; - constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011"; - constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100"; - constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101"; - constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110"; - constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111"; - constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000"; - constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001"; - constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010"; - constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011"; - constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100"; - constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101"; - constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110"; - constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111"; - - signal CONFIG_ADDR :std_logic_vector(7 downto 0); - signal CONFIG_WRITE :std_logic_vector(3 downto 0); - - -begin - - --******************************************************************* - --******************* PCI Write Configuration Address *************** - --******************************************************************* - - CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0); - - - process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) - begin - - if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then - - if CONFIG_ADDR = X"04" then - CONFIG_WRITE <= "0001"; - - elsif CONFIG_ADDR = X"10" then - CONFIG_WRITE <= "0010"; - - elsif CONFIG_ADDR = X"3C" then - CONFIG_WRITE <= "0100"; - - -- elsif CONFIG_ADDR = X"40" then - -- CONFIG_WRITE <= "1000"; - else - CONFIG_WRITE <= "0000"; - end if; - else - CONFIG_WRITE <= "0000"; - end if; - end process; - - CONF_WR_04H <= CONFIG_WRITE(0); - CONF_WR_10H <= CONFIG_WRITE(1); - CONF_WR_3CH <= CONFIG_WRITE(2); - --CONF_WR_40H <= CONFIG_WRITE(3); - -end architecture CONFIG_WR_0_DESIGN; diff --git a/dhwk/source/pci/config_00h.vhd b/dhwk/source/pci/config_00h.vhd new file mode 100644 index 0000000..98b4532 --- /dev/null +++ b/dhwk/source/pci/config_00h.vhd @@ -0,0 +1,28 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_00H.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_00H is + port + ( + VENDOR_ID :in std_logic_vector (15 downto 0); + CONF_DATA_00H :out std_logic_vector (31 downto 0) + ); +end entity CONFIG_00H; + +architecture CONFIG_00H_DESIGN of CONFIG_00H is + + -- PCI Configuration Space Header Addr : HEX 00 -- + + constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--???? + --constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--???? + +begin + + CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; + +end architecture CONFIG_00H_DESIGN; diff --git a/dhwk/source/pci/config_04h.vhd b/dhwk/source/pci/config_04h.vhd new file mode 100644 index 0000000..70d0c9f --- /dev/null +++ b/dhwk/source/pci/config_04h.vhd @@ -0,0 +1,113 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_04H.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_04H is + port + ( + PCI_CLOCK :in std_logic; + PCI_RSTn :in std_logic; + SERR :in std_logic; + PERR :in std_logic; + AD_REG :in std_logic_vector(31 downto 0); + CBE_REGn :in std_logic_vector( 3 downto 0); + CONF_WR_04H :in std_logic; + CONF_DATA_04H :out std_logic_vector(31 downto 0) + ); +end entity CONFIG_04H; + +architecture CONFIG_04H_DESIGN of CONFIG_04H is + + signal CONF_STATUS :std_logic_vector(31 downto 16); + signal CONF_COMMAND :std_logic_vector(15 downto 0); + +begin + + --******************************************************************* + --************* PCI Configuration Space Header "STATUS" ************* + --******************************************************************* + + CONF_STATUS(20 downto 16) <= "00000";-- Reserved + CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz + CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O" + CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back + CONF_STATUS(24 ) <= '0';-- Master : + --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL" + CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL" + --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL" + --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved + CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort + CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort + CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort + --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR + --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR + + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + CONF_STATUS(30) <= '0'; + CONF_STATUS(31) <= '0'; + + elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then + CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); + CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); + + else + CONF_STATUS(30) <= SERR or CONF_STATUS(30); + CONF_STATUS(31) <= PERR or CONF_STATUS(31); + + end if; + end if; +end process; + + --******************************************************************* + --*********** PCI Configuration Space Header "COMMAND" ************** + --******************************************************************* + +-- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ??? +-- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ??? +-- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus +-- CONF_COMMAND( 3) <= '0';-- Special Cycle ??? +-- CONF_COMMAND( 4) <= '0';-- Master ??? +-- CONF_COMMAND( 5) <= '0';-- VGA ??? +-- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable +CONF_COMMAND( 7) <= '0';-- address/data stepping ??? +-- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn" +-- CONF_COMMAND( 9) <= '0';-- fast back-to-back +-- CONF_COMMAND(10) <= '0';-- Reserved +-- CONF_COMMAND(11) <= '0';-- Reserved +-- CONF_COMMAND(12) <= '0';-- Reserved +-- CONF_COMMAND(13) <= '0';-- Reserved +-- CONF_COMMAND(14) <= '0';-- Reserved +-- CONF_COMMAND(15) <= '0';-- Reserved + +process (PCI_CLOCK,PCI_RSTn) +begin + if PCI_RSTn = '0' then + CONF_COMMAND(15 downto 8) <= (others =>'0'); + CONF_COMMAND( 6 downto 0) <= (others =>'0'); + + elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + + if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then + CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); + else + CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8); + end if; + + if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then + CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0); + else + CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0); + end if; + end if; +end process; + +CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; + +end architecture CONFIG_04H_DESIGN; diff --git a/dhwk/source/pci/config_08h.vhd b/dhwk/source/pci/config_08h.vhd new file mode 100644 index 0000000..7b19df6 --- /dev/null +++ b/dhwk/source/pci/config_08h.vhd @@ -0,0 +1,28 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_08H.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_08H is + port + ( + REVISION_ID :in std_logic_vector ( 7 downto 0); + CONF_DATA_08H :out std_logic_vector (31 downto 0) + ); +end entity CONFIG_08H; + +architecture CONFIG_08H_DESIGN of CONFIG_08H is + + -- PCI Configuration Space Header Addr : HEX 08 -- + + constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";--other comm. device + --constant CONF_REVISION_ID :std_logic_vector ( 7 downto 0) := X"00"; + +begin + + CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; + +end architecture CONFIG_08H_DESIGN; diff --git a/dhwk/source/pci/config_10h.vhd b/dhwk/source/pci/config_10h.vhd new file mode 100644 index 0000000..ad55b17 --- /dev/null +++ b/dhwk/source/pci/config_10h.vhd @@ -0,0 +1,77 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_10H.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_10H is + port + ( + PCI_CLOCK :in std_logic; + PCI_RSTn :in std_logic; + AD_REG :in std_logic_vector(31 downto 0); + CBE_REGn :in std_logic_vector( 3 downto 0); + CONF_WR_10H :in std_logic; + CONF_DATA_10H :out std_logic_vector(31 downto 0) + ); +end entity CONFIG_10H; + +architecture CONFIG_10H_DESIGN of CONFIG_10H is + + signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0); + +begin + + --******************************************************************* + --***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ****** + --******************************************************************* + + CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O" + CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE + + process (PCI_CLOCK,PCI_RSTn) + begin + + -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0'); + if PCI_RSTn = '0' then + CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0'); + + elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + + if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then + CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24); + else + CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24); + end if; + + if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then + CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16); + else + CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16); + end if; + + if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then + CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8); + else + CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8); + end if; + + -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then + -- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2); + -- else + -- CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2); + -- end if; + + if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then + CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4); + else + CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4); + end if; + end if; +end process; + +CONF_DATA_10H <= CONF_BAS_ADDR_REG; + +end architecture CONFIG_10H_DESIGN; diff --git a/dhwk/source/pci/config_3Ch.vhd b/dhwk/source/pci/config_3Ch.vhd new file mode 100644 index 0000000..2c79f4f --- /dev/null +++ b/dhwk/source/pci/config_3Ch.vhd @@ -0,0 +1,59 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_3CH.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_3CH is + port ( + PCI_CLOCK :in std_logic; + PCI_RSTn :in std_logic; + AD_REG :in std_logic_vector (31 downto 0); + CBE_REGn :in std_logic_vector ( 3 downto 0); + CONF_WR_3CH :in std_logic; + CONF_DATA_3CH :out std_logic_vector (31 downto 0) + ); +end entity CONFIG_3CH; + +architecture CONFIG_3CH_DESIGN of CONFIG_3CH is + + -- PCI Configuration Space Header Addr : HEX 3C -- + + signal CONF_MAX_LAT :std_logic_vector (31 downto 24); + signal CONF_MIN_GNT :std_logic_vector (23 downto 16); + signal CONF_INT_PIN :std_logic_vector (15 downto 8); + signal CONF_INT_LINE :std_logic_vector ( 7 downto 0); + + constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011"; +begin + + --******************************************************************* + --*********** PCI Configuration Space Header "INTERRUPT" ************ + --******************************************************************* + + CONF_MAX_LAT <= X"00"; + CONF_MIN_GNT <= X"00"; + -- CONF_INT_PIN <= X"00"; -- Interrupt - + CONF_INT_PIN <= X"01"; -- Interrupt A + -- CONF_INT_PIN <= X"02"; -- Interrupt B + -- CONF_INT_PIN <= X"03"; -- Interrupt C + -- CONF_INT_PIN <= X"04"; -- Interrupt D + -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert + + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + CONF_INT_LINE <= (others => '0'); + + elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then + CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0); + end if; + end if; + end process; + + CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE; + +end architecture CONFIG_3CH_DESIGN; diff --git a/dhwk/source/pci/config_mux_0.vhd b/dhwk/source/pci/config_mux_0.vhd new file mode 100644 index 0000000..f1b34f7 --- /dev/null +++ b/dhwk/source/pci/config_mux_0.vhd @@ -0,0 +1,43 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_MUX_0.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_MUX_0 is + port + ( + READ_SEL :in std_logic_vector( 2 downto 0); + CONF_DATA_00H :in std_logic_vector(31 downto 0); + CONF_DATA_04H :in std_logic_vector(31 downto 0); + CONF_DATA_08H :in std_logic_vector(31 downto 0); + CONF_DATA_10H :in std_logic_vector(31 downto 0); + CONF_DATA_3CH :in std_logic_vector(31 downto 0); + --CONF_DATA_40H :in std_logic_vector(31 downto 0); + CONF_DATA :out std_logic_vector(31 downto 0) + ); +end entity CONFIG_MUX_0; + +architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is + + signal MUX :std_logic_vector (31 downto 0); + +begin + + --******************************************************************* + --******************* PCI Read Config-MUX ************************** + --******************************************************************* + + MUX <= CONF_DATA_00H when READ_SEL <= "000" else + CONF_DATA_04H when READ_SEL <= "001" else + CONF_DATA_08H when READ_SEL <= "010" else + CONF_DATA_10H when READ_SEL <= "011" else + CONF_DATA_3CH when READ_SEL <= "100" else + -- CONF_DATA_40H when READ_SEL <= "101" else + X"00000000"; + + CONF_DATA <= MUX; + +end architecture CONFIG_MUX_0_DESIGN; diff --git a/dhwk/source/pci/config_rd_0.vhd b/dhwk/source/pci/config_rd_0.vhd new file mode 100644 index 0000000..92b6a98 --- /dev/null +++ b/dhwk/source/pci/config_rd_0.vhd @@ -0,0 +1,134 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_RD_0.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_RD_0 is + port + ( + ADDR_REG :in std_logic_vector (31 downto 0); + CF_RD_COM :in std_logic; + READ_SEL :out std_logic_vector ( 2 downto 0) + ); +end entity CONFIG_RD_0; + +architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is + + -- + -- + -- + -- + -- + -- PCI Configuration Space Header + -- + -- \ Bit + -- \ + --Address |31 24|23 16|15 8|7 0| + ----------------------------------------------------------------- + --00 |Device ID |Vendor ID | + --04 |Status |Command | + --08 |Class Code |Revision ID| + --0C |BIST |Header Type|Latency T. |Cache L.S. | + --10-24 |Base Address Register | + --28 |Cardbus CIS Pointer | + --2C |Subsystem ID |Subsystem Vendor ID | + --30 |Expansion ROM Base Address | + --34 |Reserved | + --38 |Reserved | + --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line | + --40-FF | | + ----------------------------------------------------------------- + + + --PCI Bus Commands + --C/BE[3..0] Command Type + -------------------------------------- + -- 0000 Interrupt Acknowledge + -- 0001 Special Cycle + -- 0010 I/O Read + -- 0011 I/O Write + -- 0100 Reserved + -- 0101 Reserved + -- 0110 Memory Read + -- 0111 Memory Write + -- + -- 1000 Reserved + -- 1001 Reserved + -- 1010 Configuration Read + -- 1011 Configuration Write + -- 1100 Memory Read Multiple + -- 1101 Dual Address Cycle + -- 1110 Memory Read Line + -- 1111 Memory Write and Invalidate + + + --PCI Byte Enable + --C/BE[3..0] gueltige Datenbits + ------------------------------- + -- 0000 AD 31..0 + -- 1000 AD 23..0 + -- 1100 AD 15..0 + -- 1110 AD 7..0 + + constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000"; + constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001"; + constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010"; + constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011"; + constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100"; + constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101"; + constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110"; + constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111"; + constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000"; + constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001"; + constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010"; + constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011"; + constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100"; + constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101"; + constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110"; + constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111"; + + signal MUX :std_logic_vector(31 downto 0); + signal CONFIG_ADDR :std_logic_vector( 7 downto 0); + +begin + + CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0); + + --******************************************************************* + --*********************** PCI Read Address ************************** + --******************************************************************* + + process (CF_RD_COM, CONFIG_ADDR) + begin + + if CF_RD_COM = '1' then + if CONFIG_ADDR = X"00" then + READ_SEL <= "000"; + + elsif CONFIG_ADDR = X"04" then + READ_SEL <= "001"; + + elsif CONFIG_ADDR = X"08" then + READ_SEL <= "010"; + + elsif CONFIG_ADDR = X"10" then + READ_SEL <= "011"; + + elsif CONFIG_ADDR = X"3C" then + READ_SEL <= "100"; + + elsif CONFIG_ADDR = X"40" then + READ_SEL <= "101"; + + else + READ_SEL <= "111"; + end if; + else + READ_SEL <= "111"; + end if; + end process; + +end architecture CONFIG_RD_0_DESIGN; diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd new file mode 100644 index 0000000..15db761 --- /dev/null +++ b/dhwk/source/pci/config_space_header.vhd @@ -0,0 +1,155 @@ +-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007 + +LIBRARY ieee; + +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +entity CONFIG_SPACE_HEADER is + Port ( AD_REG : In std_logic_vector (31 downto 0); + ADDR_REG : In std_logic_vector (31 downto 0); + CBE_REGn : In std_logic_vector (3 downto 0); + CF_RD_COM : In std_logic; + CF_WR_COM : In std_logic; + IRDY_REGn : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + PERR : In std_logic; + REVISION_ID : In std_logic_vector (7 downto 0); + SERR : In std_logic; + TRDYn : In std_logic; + VENDOR_ID : In std_logic_vector (15 downto 0); + CONF_DATA : Out std_logic_vector (31 downto 0); + CONF_DATA_04H : Out std_logic_vector (31 downto 0); + CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); +end CONFIG_SPACE_HEADER; + +architecture SCHEMATIC of CONFIG_SPACE_HEADER is + + SIGNAL gnd : std_logic := '0'; + SIGNAL vcc : std_logic := '1'; + + signal CONF_WR_04H : std_logic; + signal CONF_WR_10H : std_logic; + signal CONF_WR_3CH : std_logic; + signal CONF_READ_SEL : std_logic_vector (2 downto 0); + signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0); + signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0); + signal CONF_DATA_3CH : std_logic_vector (31 downto 0); + signal CONF_DATA_08H : std_logic_vector (31 downto 0); + signal CONF_DATA_00H : std_logic_vector (31 downto 0); + + component CONFIG_MUX_0 + Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0); + CONF_DATA_04H : In std_logic_vector (31 downto 0); + CONF_DATA_08H : In std_logic_vector (31 downto 0); + CONF_DATA_10H : In std_logic_vector (31 downto 0); + CONF_DATA_3CH : In std_logic_vector (31 downto 0); + READ_SEL : In std_logic_vector (2 downto 0); + CONF_DATA : Out std_logic_vector (31 downto 0) ); + end component; + + component CONFIG_RD_0 + Port ( ADDR_REG : In std_logic_vector (31 downto 0); + CF_RD_COM : In std_logic; + READ_SEL : Out std_logic_vector (2 downto 0) ); + end component; + + component CONFIG_WR_0 + Port ( ADDR_REG : In std_logic_vector (31 downto 0); + CF_WR_COM : In std_logic; + IRDY_REGn : In std_logic; + TRDYn : In std_logic; + CONF_WR_04H : Out std_logic; + CONF_WR_10H : Out std_logic; + CONF_WR_3CH : Out std_logic ); + end component; + + component CONFIG_3CH + Port ( AD_REG : In std_logic_vector (31 downto 0); + CBE_REGn : In std_logic_vector (3 downto 0); + CONF_WR_3CH : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + CONF_DATA_3CH : Out std_logic_vector (31 downto 0) ); + end component; + + component CONFIG_10H + Port ( AD_REG : In std_logic_vector (31 downto 0); + CBE_REGn : In std_logic_vector (3 downto 0); + CONF_WR_10H : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); + end component; + + component CONFIG_08H + Port ( REVISION_ID : In std_logic_vector (7 downto 0); + CONF_DATA_08H : Out std_logic_vector (31 downto 0) ); + end component; + + component CONFIG_00H + Port ( VENDOR_ID : In std_logic_vector (15 downto 0); + CONF_DATA_00H : Out std_logic_vector (31 downto 0) ); + end component; + + component CONFIG_04H + Port ( AD_REG : In std_logic_vector (31 downto 0); + CBE_REGn : In std_logic_vector (3 downto 0); + CONF_WR_04H : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + PERR : In std_logic; + SERR : In std_logic; + CONF_DATA_04H : Out std_logic_vector (31 downto 0) ); + end component; + +begin + + CONF_DATA_04H <= CONF_DATA_04H_DUMMY; + CONF_DATA_10H <= CONF_DATA_10H_DUMMY; + + I10 : CONFIG_MUX_0 + Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0), + CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0), + CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0), + CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0), + CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0), + READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0), + CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) ); + I9 : CONFIG_RD_0 + Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), + CF_RD_COM=>CF_RD_COM, + READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) ); + I8 : CONFIG_WR_0 + Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), + CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn, + TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H, + CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH ); + I6 : CONFIG_3CH + Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), + CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), + CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK, + PCI_RSTn=>PCI_RSTn, + CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) ); + I5 : CONFIG_10H + Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), + CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), + CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK, + PCI_RSTn=>PCI_RSTn, + CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) ); + I4 : CONFIG_08H + Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0), + CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) ); + I3 : CONFIG_00H + Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0), + CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) ); + I2 : CONFIG_04H + Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), + CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), + CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK, + PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR, + CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) ); + +end SCHEMATIC; diff --git a/dhwk/source/pci/config_wr_0.vhd b/dhwk/source/pci/config_wr_0.vhd new file mode 100644 index 0000000..9e1e2dc --- /dev/null +++ b/dhwk/source/pci/config_wr_0.vhd @@ -0,0 +1,140 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 23.08.2006 +-- File: CONFIG_WR_0.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity CONFIG_WR_0 is + port + ( + ADDR_REG :in std_logic_vector(31 downto 0); + CF_WR_COM :in std_logic; + IRDY_REGn :in std_logic; + TRDYn :in std_logic; + CONF_WR_04H :out std_logic; + CONF_WR_10H :out std_logic; + CONF_WR_3CH :out std_logic + --CONF_WR_40H :out std_logic + ); +end entity CONFIG_WR_0; + +architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is + + -- + -- + -- + -- + -- + -- PCI Configuration Space Header + -- + -- \ Bit + -- \ + --Address |31 24|23 16|15 8|7 0| + ----------------------------------------------------------------- + --00 |Device ID |Vendor ID | + --04 |Status |Command | + --08 |Class Code |Revision ID | + --0C |BIST |Header Type |Latency T. |Cache L.S. | + --10-24 |Base Address Register | + --28 |Cardbus CIS Pointer | + --2C |Subsystem ID |Subsystem Vendor ID | + --30 |Expansion ROM Base Address | + --34 |Reserved | + --38 |Reserved | + --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line | + --40-FF | | + ----------------------------------------------------------------- + + + --PCI Bus Commands + --C/BE[3..0] Command Type + -------------------------------------- + -- 0000 Interrupt Acknowledge + -- 0001 Special Cycle + -- 0010 I/O Read + -- 0011 I/O Write + -- 0100 Reserved + -- 0101 Reserved + -- 0110 Memory Read + -- 0111 Memory Write + -- + -- 1000 Reserved + -- 1001 Reserved + -- 1010 Configuration Read + -- 1011 Configuration Write + -- 1100 Memory Read Multiple + -- 1101 Dual Address Cycle + -- 1110 Memory Read Line + -- 1111 Memory Write and Invalidate + + + --PCI Byte Enable + --C/BE[3..0] gueltige Datenbits + ------------------------------- + -- 0000 AD 31..0 + -- 1000 AD 23..0 + -- 1100 AD 15..0 + -- 1110 AD 7..0 + + constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000"; + constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001"; + constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010"; + constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011"; + constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100"; + constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101"; + constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110"; + constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111"; + constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000"; + constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001"; + constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010"; + constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011"; + constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100"; + constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101"; + constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110"; + constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111"; + + signal CONFIG_ADDR :std_logic_vector(7 downto 0); + signal CONFIG_WRITE :std_logic_vector(3 downto 0); + + +begin + + --******************************************************************* + --******************* PCI Write Configuration Address *************** + --******************************************************************* + + CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0); + + + process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) + begin + + if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then + + if CONFIG_ADDR = X"04" then + CONFIG_WRITE <= "0001"; + + elsif CONFIG_ADDR = X"10" then + CONFIG_WRITE <= "0010"; + + elsif CONFIG_ADDR = X"3C" then + CONFIG_WRITE <= "0100"; + + -- elsif CONFIG_ADDR = X"40" then + -- CONFIG_WRITE <= "1000"; + else + CONFIG_WRITE <= "0000"; + end if; + else + CONFIG_WRITE <= "0000"; + end if; + end process; + + CONF_WR_04H <= CONFIG_WRITE(0); + CONF_WR_10H <= CONFIG_WRITE(1); + CONF_WR_3CH <= CONFIG_WRITE(2); + --CONF_WR_40H <= CONFIG_WRITE(3); + +end architecture CONFIG_WR_0_DESIGN;