From: sithglan Date: Sun, 11 Mar 2007 09:05:56 +0000 (+0000) Subject: Adding a test bench back that isn't a test bench. I shouldn't have deleted in X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/0c81dc03729a06b725c12c2d39632f5749eee02c?ds=inline Adding a test bench back that isn't a test bench. I shouldn't have deleted in the first place because all real testbenches were gone by yesterday. --- diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj index 0429c18..113fec6 100644 --- a/dhwk/dhwk.prj +++ b/dhwk/dhwk.prj @@ -23,6 +23,7 @@ vhdl work "source/pci/io_mux.vhd" vhdl work "source/pci/io_mux_reg.vhd" vhdl work "source/pci/io_reg.vhd" vhdl work "source/pci/io_rw_sel.vhd" +vhdl work "source/pci/mess_tb.vhd" vhdl work "source/pci/parity.vhd" vhdl work "source/pci/parity_4.vhd" vhdl work "source/pci/parity_out.vhd" diff --git a/dhwk/source/pci/mess_tb.vhd b/dhwk/source/pci/mess_tb.vhd new file mode 100644 index 0000000..ec9b512 --- /dev/null +++ b/dhwk/source/pci/mess_tb.vhd @@ -0,0 +1,33 @@ +-- J.STELZNER +-- INFORMATIK-3 LABOR +-- 29.08.2006 +-- File: MESS_1_TB.VHD + +library IEEE; +use IEEE.std_logic_1164.all; + +entity MESS_1_TB is + port + ( + KONST_1 :in std_logic; + PCI_IDSEL :in std_logic; + DEVSELn :in std_logic; + INTAn :in std_logic; + REG_OUT_XX7 :in std_logic_vector(7 downto 0); + TB_PCI_IDSEL :out std_logic; + TB_DEVSELn :out std_logic; + TB_INTAn :out std_logic + ); +end entity MESS_1_TB; + +architecture MESS_1_TB_DESIGN of MESS_1_TB is + +begin + + TB_PCI_IDSEL <= PCI_IDSEL and KONST_1; + + TB_INTAn <= INTAn and KONST_1; + + TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6)); + +end architecture MESS_1_TB_DESIGN;