From: michael <michael>
Date: Sat, 10 Mar 2007 21:23:22 +0000 (+0000)
Subject: remove build fifo, ila and icon
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/12bc1626ea861c69fbbd136ae81e4d7f0055ab9f?hp=114b8f219f285141d24524c81fb640048a77c23c

remove build fifo, ila and icon
add rules to build fifo, ila and icon
---

diff --git a/common/Makefile.common b/common/Makefile.common
index 5bea6cc..534fe6d 100644
--- a/common/Makefile.common
+++ b/common/Makefile.common
@@ -78,7 +78,7 @@ flash: $(PROJECT)-xcf02s.mcs $(PROJECT)-xcf04s.mcs
 	@rm xcf.batch.tmp
 
 clean:
-	@rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd \
+	@rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd *.edn \
 		*.ngr *.pad *.par *.pcf *.prm *.syr *.twr *.twx *.xpi *.lso *.prm *.mcs _impact* \
 		*.vm6 *.jed *.gyd *.mfd *.pnx *.rpt *.err \
 		$(PROJECT)_map.* $(PROJECT)_pad.* \
diff --git a/dhwk/Makefile b/dhwk/Makefile
index b3cd515..063973d 100644
--- a/dhwk/Makefile
+++ b/dhwk/Makefile
@@ -1,3 +1,16 @@
 PROJECT := dhwk
 
+dhwk_all: ip all
+
+ip: icon.edn ila.edn fifo_generator_v3_2.ngc
+
+icon.edn: icon.arg
+	$(CHIPSCOPE)/bin/lin/generate.sh icon -f=$<
+
+ila.edn: ila.arg
+	$(CHIPSCOPE)/bin/lin/generate.sh ila -f=$<
+
+fifo_generator_v3_2.ngc: fifo_generator_v3_2.xco
+	coregen -b $<
+
 include ../common/Makefile.common
diff --git a/dhwk/fifo.xco b/dhwk/fifo.xco
new file mode 100644
index 0000000..8dde1a2
--- /dev/null
+++ b/dhwk/fifo.xco
@@ -0,0 +1,76 @@
+##############################################################
+#
+# Xilinx Core Generator version J.30
+# Date: Sat Mar 10 21:20:43 2007
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s1500
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 3.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=true
+CSET almost_full_flag=true
+CSET component_name=fifo_generator_v3_2
+CSET data_count=false
+CSET data_count_width=12
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_threshold_assert_value=2048
+CSET full_threshold_negate_value=2047
+CSET input_data_width=8
+CSET input_depth=4096
+CSET output_data_width=8
+CSET output_depth=4096
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=100
+CSET read_data_count=false
+CSET read_data_count_width=12
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=100
+CSET write_data_count=false
+CSET write_data_count_width=12
+# END Parameters
+GENERATE
+# CRC: c795162c
+