From: michael <michael>
Date: Sat, 10 Feb 2007 15:58:08 +0000 (+0000)
Subject: += heartbeat
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/152884e67f2cea6ff9f5787eab6c72dcffe484e4
+= heartbeat
---
diff --git a/heartbeat/Makefile b/heartbeat/Makefile
index b0ba87c..0399ea3 100644
--- a/heartbeat/Makefile
+++ b/heartbeat/Makefile
@@ -19,7 +19,7 @@ ngdbuild: $(PROJECT).ngc $(PROJECT).ngd
$(PROJECT).ngc:
@# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1
echo work > $(PROJECT).lso
- xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr &> tmp/build.xst.log
+ xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr
#cat $(PROJECT).syr
mv $(PROJECT).syr $(TMP)
mv $(PROJECT).ngr $(PROJECT).lso $(TMP)
diff --git a/heartbeat/raggedstone.prj b/heartbeat/raggedstone.prj
index 2c8b3d8..e0adeac 100644
--- a/heartbeat/raggedstone.prj
+++ b/heartbeat/raggedstone.prj
@@ -1,6 +1,4 @@
verilog work "source/sync.v"
-verilog work "source/disp_dec.v"
-verilog work "source/wb_7seg.v"
verilog work "source/pcidec.v"
verilog work "source/pcidmux.v"
@@ -12,5 +10,5 @@ vhdl work "source/pfs.vhd"
vhdl work "source/new_pciregs.vhd"
vhdl work "source/pcipargen.vhd"
vhdl work "source/new_pci32tlite.vhd"
-vhdl work "source/vga_main.vhd"
vhdl work "source/top_pci_7seg.vhd"
+vhdl work "source/heartbeat.vhd"
diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 483a19f..31d028c 100644
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -1,14 +1,3 @@
-NET "DISP_LED<0>" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<1>" LOC = "AA20" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<2>" LOC = "V18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<3>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<4>" LOC = "AB18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<5>" LOC = "AA18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<6>" LOC = "W18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<0>" LOC = "AA17" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<1>" LOC = "U17" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<2>" LOC = "U16" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<3>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "LED_ACCESS" LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
NET "LED_INIT" LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
NET "PCI_AD<0>" LOC = "A5" | IOSTANDARD = PCI33_3 ;
@@ -60,9 +49,3 @@ NET "PCI_nSTOP" LOC = "A12" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_nTRDY" LOC = "B13" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "LED_ALIVE" LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
-NET "mclk" LOC = "E22";
-NET "red" LOC = "E21";
-NET "grn" LOC = "F21";
-NET "blu" LOC = "F20";
-NET "hs" LOC = "F19";
-NET "vs" LOC = "G19";
diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
new file mode 100644
index 0000000..76f084d
--- /dev/null
+++ b/heartbeat/source/heartbeat.vhd
@@ -0,0 +1,39 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity heartbeat is
+generic (
+ divider : integer := 33000000
+);
+
+port (
+ clk_i : in std_logic;
+ nrst_i : in std_logic;
+ led_o : out std_logic
+);
+
+end heartbeat;
+
+architecture rtl of heartbeat is
+begin
+
+process(clk_i, nrst_i)
+variable counter : std_logic_vector(31 downto 0);
+variable state : std_logic := '0';
+begin
+
+if (clk_i'event AND clk_i = '1') then
+ if nrst_i = '0' then
+ counter := (others => '0');
+ else
+ led_o <= state;
+ counter := counter + 1;
+ if counter = divider then
+ state := not state;
+ end if;
+ end if;
+end if;
+end process;
+end architecture;
diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 6b449a7..73fefb1 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -59,20 +59,10 @@ port (
PCI_nSERR : out std_logic;
PCI_nINT : out std_logic;
- -- 7seg
- DISP_SEL : inout std_logic_vector(3 downto 0);
- DISP_LED : out std_logic_vector(6 downto 0);
-
-- debug signals
LED_INIT : out std_logic;
LED_ACCESS : out std_logic;
- LED_ALIVE : out std_logic;
-
- -- vga signals
- hs : out std_logic;
- vs : out std_logic;
- red, grn, blu : out std_logic;
- mclk : in std_logic
+ LED_ALIVE : out std_logic
);
end pci_7seg;
@@ -129,41 +119,12 @@ port (
);
end component;
-
-component wb_7seg_new
+component heartbeat
port (
-
- -- General
- clk_i : in std_logic;
- nrst_i : in std_logic;
-
- -- Master whisbone
- wb_adr_i : in std_logic_vector(24 downto 1);
- wb_dat_o : out std_logic_vector(15 downto 0);
- wb_dat_i : in std_logic_vector(15 downto 0);
- wb_sel_i : in std_logic_vector(1 downto 0);
- wb_we_i : in std_logic;
- wb_stb_i : in std_logic;
- wb_cyc_i : in std_logic;
- wb_ack_o : out std_logic;
- wb_err_o : out std_logic;
- wb_int_o : out std_logic;
-
- -- 7seg
- DISP_SEL : inout std_logic_vector(3 downto 0);
- DISP_LED : out std_logic_vector(6 downto 0)
-
- );
-end component;
-
-
-component vgaController is
- Port ( mclk : in std_logic;
- hs : out std_logic;
- vs : out std_logic;
- red : out std_logic;
- grn : out std_logic;
- blu : out std_logic);
+ clk_i : in std_logic;
+ nrst_i : in std_logic;
+ led_o : out std_logic
+);
end component;
@@ -188,18 +149,6 @@ end component;
begin
- LED_ALIVE <= '1';
---+-------------------------------------------------------------------------+
---| Component instances |
---+-------------------------------------------------------------------------+
-
- vga1: vgaController port map (mclk => mclk,
- hs => hs,
- vs => vs,
- red => red,
- grn => grn,
- blu => blu);
-
--+-----------------------------------------+
--| PCI Target |
--+-----------------------------------------+
@@ -238,22 +187,11 @@ port map(
--| WB-7seg |
--+-----------------------------------------+
-u_wb: component wb_7seg_new
-port map(
- clk_i => PCI_CLK,
- nrst_i => PCI_nRES,
- wb_adr_i => wb_adr,
- wb_dat_o => wb_dat_out,
- wb_dat_i => wb_dat_in,
- wb_sel_i => wb_sel,
- wb_we_i => wb_we,
- wb_stb_i => wb_stb,
- wb_cyc_i => wb_cyc,
- wb_ack_o => wb_ack,
- wb_err_o => wb_err,
- wb_int_o => wb_int,
- DISP_SEL => DISP_SEL,
- DISP_LED => DISP_LED
+my_heartbeat: component heartbeat
+port map(
+ clk_i => PCI_CLK,
+ nrst_i => PCI_nRES,
+ led_o => LED_ALIVE
);
end pci_7seg_arch;