From: michael <michael>
Date: Sat, 10 Mar 2007 18:08:57 +0000 (+0000)
Subject: larger ila
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/1cc8dbebf4ad3ef2d28da957b2830483b2089452?ds=sidebyside

larger ila
---

diff --git a/dhwk/ila.arg b/dhwk/ila.arg
index 2d1a318..2433cb4 100644
--- a/dhwk/ila.arg
+++ b/dhwk/ila.arg
@@ -3,10 +3,10 @@
 #
 -compname=ila
 -outputdirectory=.
--datadepth=8192
--datawidth=36
+-datadepth=4096
+-datawidth=96
 -numtrigports=1
--trigportwidth0=8
+-trigportwidth0=32
 -nummatchunits=1
 -mtrigport0=0
 -mtype0=0
diff --git a/dhwk/source/config_3Ch.vhd b/dhwk/source/config_3Ch.vhd
index 642a484..5b7ef41 100644
--- a/dhwk/source/config_3Ch.vhd
+++ b/dhwk/source/config_3Ch.vhd
@@ -27,6 +27,8 @@ architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
 	signal		CONF_INT_PIN		:std_logic_vector (15 downto  8);
 	signal		CONF_INT_LINE		:std_logic_vector ( 7 downto  0);  
 
+	constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";
+
 begin 
 
 --*******************************************************************
diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 4becb68..5258c3a 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(35 downto 0);
-   signal trig0      : std_logic_vector(7 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -236,8 +236,8 @@ end component;
     (
       control     : in    std_logic_vector(35 downto 0);
       clk         : in    std_logic;
-      data        : in    std_logic_vector(35 downto 0);
-      trig0       : in    std_logic_vector(7 downto 0)
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
     );
   end component;
 
@@ -250,7 +250,7 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
+	trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
 	data(0) <= watch;
 	
 	data(1) <= R_EFn;
@@ -273,6 +273,7 @@ begin
 	data(18) <= SPC_RDY_OUT;
 	data(26 downto 19) <= S_FIFO_Q_OUT;
 	data(34 downto 27) <= R_FIFO_Q_OUT;
+	data(66 downto 35) <= PCI_AD(31 downto 0);
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,