From: michael Date: Sun, 11 Mar 2007 23:19:47 +0000 (+0000) Subject: working vio X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/1e992b68223013ce0de071f408689ab8dc1ec4d3 working vio it's now possible to send interrupts from within chipscope --- diff --git a/common/Makefile.common b/common/Makefile.common index bbf4218..6d17bad 100644 --- a/common/Makefile.common +++ b/common/Makefile.common @@ -85,7 +85,7 @@ analyzer: $(CHIPSCOPE)/bin/lin/analyzer.sh -project $(PWD)/$(PROJECT).cpj clean: - @rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd *.edn *.ncf *.ngo *.cdc \ + @rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd *.edn *.ncf *.ngo \ *.ngr *.pad *.par *.pcf *.prm *.syr *.twr *.twx *.xpi *.lso *.prm *.mcs _impact* \ *.vm6 *.jed *.gyd *.mfd *.pnx *.rpt *.err *.log \ $(PROJECT)_map.* $(PROJECT)_pad.* \ diff --git a/dhwk/dhwk.cpj b/dhwk/dhwk.cpj index 1d38452..81928a1 100644 --- a/dhwk/dhwk.cpj +++ b/dhwk/dhwk.cpj @@ -1,5 +1,5 @@ #ChipScope Pro Analyzer Project File, Version 3.0 -#Sun Mar 11 16:35:40 GMT+01:00 2007 +#Mon Mar 12 00:15:32 GMT+01:00 2007 deviceChain.deviceName0=XCF02S deviceChain.deviceName1=XCF04S deviceChain.deviceName2=XC3S1500 @@ -10,8 +10,8 @@ deviceChain.name0=MyDevice0 deviceChain.name1=MyDevice1 deviceChain.name2=MyDevice2 deviceIds=050450930504609301434093 -mdiAreaHeight=0.8329383886255924 -mdiAreaHeightLast=0.8696682464454977 +mdiAreaHeight=0.8411330049261084 +mdiAreaHeightLast=0.8780788177339901 mdiCount=3 mdiDevice0=2 mdiDevice1=2 @@ -22,22 +22,22 @@ mdiType2=0 mdiUnit0=1 mdiUnit1=0 mdiUnit2=0 -navigatorHeight=0.17061611374407584 -navigatorHeightLast=0.17061611374407584 -navigatorWidth=0.1803921568627451 -navigatorWidthLast=0.1803921568627451 +navigatorHeight=0.17118226600985223 +navigatorHeightLast=0.17118226600985223 +navigatorWidth=0.1816326530612245 +navigatorWidthLast=0.1816326530612245 unit.-1.-1.username= -unit.2.0.0.HEIGHT0=0.2942857 +unit.2.0.0.HEIGHT0=0.30294117 unit.2.0.0.TriggerRow0=1 unit.2.0.0.TriggerRow1=1 unit.2.0.0.TriggerRow2=1 -unit.2.0.0.WIDTH0=0.99757284 +unit.2.0.0.WIDTH0=0.99746835 unit.2.0.0.X0=0.0 unit.2.0.0.Y0=0.0 -unit.2.0.1.HEIGHT1=0.7171429 -unit.2.0.1.WIDTH1=0.9987864 -unit.2.0.1.X1=-0.0012135922 -unit.2.0.1.Y1=0.28428572 +unit.2.0.1.HEIGHT1=0.7176471 +unit.2.0.1.WIDTH1=0.9987342 +unit.2.0.1.X1=-0.0012658228 +unit.2.0.1.Y1=0.28382352 unit.2.0.MFBitsA0=0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX unit.2.0.MFBitsB0=00000000000000000000000000000000 unit.2.0.MFCompareA0=0 @@ -974,17 +974,51 @@ unit.2.0.waveform.posn.9.channel=76 unit.2.0.waveform.posn.9.name=SERRn unit.2.0.waveform.posn.9.radix=1 unit.2.0.waveform.posn.9.type=signal -unit.2.1.6.HEIGHT6=0.2 -unit.2.1.6.WIDTH6=0.34951457 -unit.2.1.6.X6=0.016990291 -unit.2.1.6.Y6=0.32714286 +unit.2.1.6.HEIGHT6=0.425 +unit.2.1.6.WIDTH6=0.6126582 +unit.2.1.6.X6=0.016455697 +unit.2.1.6.Y6=0.32647058 +unit.2.1.browser_tree_state=1 +unit.2.1.browser_tree_state=1 unit.2.1.coretype=VIO unit.2.1.port.-1.buscount=0 -unit.2.1.port.-1.channelcount=0 +unit.2.1.port.-1.channelcount=4 +unit.2.1.port.-1.s.0.alias=LED_PCIReset +unit.2.1.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.1.port.-1.s.0.display=16 +unit.2.1.port.-1.s.0.name=AsyncIn[0] +unit.2.1.port.-1.s.0.orderindex=-1 +unit.2.1.port.-1.s.0.persistence=0 +unit.2.1.port.-1.s.0.value=0 +unit.2.1.port.-1.s.0.visible=1 +unit.2.1.port.-1.s.1.alias=LED_IDSEL +unit.2.1.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.1.port.-1.s.1.display=16 +unit.2.1.port.-1.s.1.name=AsyncIn[1] +unit.2.1.port.-1.s.1.orderindex=-1 +unit.2.1.port.-1.s.1.persistence=0 +unit.2.1.port.-1.s.1.value=0 +unit.2.1.port.-1.s.1.visible=1 +unit.2.1.port.-1.s.2.alias=LED_FRAME +unit.2.1.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.1.port.-1.s.2.display=16 +unit.2.1.port.-1.s.2.name=AsyncIn[2] +unit.2.1.port.-1.s.2.orderindex=-1 +unit.2.1.port.-1.s.2.persistence=0 +unit.2.1.port.-1.s.2.value=0 +unit.2.1.port.-1.s.2.visible=1 +unit.2.1.port.-1.s.3.alias=LED_INTA +unit.2.1.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.1.port.-1.s.3.display=16 +unit.2.1.port.-1.s.3.name=AsyncIn[3] +unit.2.1.port.-1.s.3.orderindex=-1 +unit.2.1.port.-1.s.3.persistence=0 +unit.2.1.port.-1.s.3.value=0 +unit.2.1.port.-1.s.3.visible=1 unit.2.1.port.0.buscount=0 unit.2.1.port.0.channelcount=0 unit.2.1.port.1.buscount=0 -unit.2.1.port.1.channelcount=1 +unit.2.1.port.1.channelcount=0 unit.2.1.port.1.s.0.alias=PCI_INTA unit.2.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] unit.2.1.port.1.s.0.display=1 @@ -994,12 +1028,36 @@ unit.2.1.port.1.s.0.persistence=0 unit.2.1.port.1.s.0.value=0 unit.2.1.port.1.s.0.visible=1 unit.2.1.port.2.buscount=0 -unit.2.1.port.2.channelcount=0 +unit.2.1.port.2.channelcount=1 +unit.2.1.port.2.s.0.alias=PCI_INTA +unit.2.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.1.port.2.s.0.display=1 +unit.2.1.port.2.s.0.name=SyncOut[0] +unit.2.1.port.2.s.0.orderindex=-1 +unit.2.1.port.2.s.0.persistence=0 +unit.2.1.port.2.s.0.value=0 +unit.2.1.port.2.s.0.visible=1 unit.2.1.portcount=3 unit.2.1.username=MyVIO1 -unit.2.1.vio.count=1 +unit.2.1.vio.count=5 unit.2.1.vio.posn.0.channel=0 -unit.2.1.vio.posn.0.name=PCI_INTA -unit.2.1.vio.posn.0.port=1 +unit.2.1.vio.posn.0.name=LED_PCIReset +unit.2.1.vio.posn.0.port=-1 unit.2.1.vio.posn.0.type=signal +unit.2.1.vio.posn.1.channel=1 +unit.2.1.vio.posn.1.name=LED_IDSEL +unit.2.1.vio.posn.1.port=-1 +unit.2.1.vio.posn.1.type=signal +unit.2.1.vio.posn.2.channel=2 +unit.2.1.vio.posn.2.name=LED_FRAME +unit.2.1.vio.posn.2.port=-1 +unit.2.1.vio.posn.2.type=signal +unit.2.1.vio.posn.3.channel=3 +unit.2.1.vio.posn.3.name=LED_INTA +unit.2.1.vio.posn.3.port=-1 +unit.2.1.vio.posn.3.type=signal +unit.2.1.vio.posn.4.channel=0 +unit.2.1.vio.posn.4.name=PCI_INTA +unit.2.1.vio.posn.4.port=2 +unit.2.1.vio.posn.4.type=signal unit.2.1.vio.readperiod=0 diff --git a/dhwk/source/pci/top.vhd b/dhwk/source/pci/top.vhd index 27cd84c..5c4851a 100644 --- a/dhwk/source/pci/top.vhd +++ b/dhwk/source/pci/top.vhd @@ -90,6 +90,7 @@ architecture SCHEMATIC of dhwk is signal SPC_RDY_IN : std_logic; signal SERIAL_OUT : std_logic; signal SPC_RDY_OUT : std_logic; + signal led_PCI_INTA : std_logic; signal watch_PCI_INTAn : std_logic; signal watch_PCI_TRDYn : std_logic; signal watch_PCI_STOPn : std_logic; @@ -100,7 +101,8 @@ architecture SCHEMATIC of dhwk is signal control1 : std_logic_vector(35 downto 0); signal data : std_logic_vector(95 downto 0); signal trig0 : std_logic_vector(31 downto 0); - signal vio_async_out : std_logic_vector(0 downto 0); + signal vio_sync_out : std_logic_vector(0 downto 0); + signal vio_async_in : std_logic_vector(3 downto 0); component MESS_1_TB Port ( DEVSELn : In std_logic; @@ -253,20 +255,36 @@ architecture SCHEMATIC of dhwk is port ( control : in std_logic_vector(35 downto 0); - async_out : out std_logic_vector(0 downto 0) + clk : in std_logic; + async_in : in std_logic_vector(3 downto 0); + sync_out : out std_logic_vector(0 downto 0) ); end component; begin + process(PCI_CLOCK) + begin + if rising_edge(PCI_CLOCK) then + led_PCI_INTA <= not (watch_PCI_INTAn and (not vio_sync_out(0))); + end if; + end process; + watch_PCI_REQn <= '1'; SERIAL_IN <= SERIAL_OUT; SPC_RDY_IN <= SPC_RDY_OUT; LED_2 <= not PCI_RSTn; LED_3 <= not PCI_IDSEL; LED_4 <= not PCI_FRAMEn; - LED_5 <= not (watch_PCI_INTAn and (not vio_async_out(0))); - PCI_INTAn <= watch_PCI_INTAn and (not vio_async_out(0)); + LED_5 <= led_PCI_INTA; + PCI_INTAn <= (watch_PCI_INTAn and (not vio_sync_out(0))); + + vio_async_in(3 downto 0) <= ( + 0 => not PCI_RSTn, + 1 => not PCI_IDSEL, + 2 => not PCI_FRAMEn, + 3 => led_PCI_INTA + ); trig0(31 downto 0) <= ( 0 => watch_PCI_INTAn, @@ -441,6 +459,8 @@ begin port map ( control => control1, - async_out => vio_async_out + clk => PCI_CLOCK, + async_in => vio_async_in, + sync_out => vio_sync_out ); end SCHEMATIC; diff --git a/dhwk/vio.arg b/dhwk/vio.arg index 44f7884..e719ad4 100644 --- a/dhwk/vio.arg +++ b/dhwk/vio.arg @@ -3,7 +3,8 @@ # -compname=vio -outputdirectory=. --devicefamily=Spartan3 +-devicefamily=Virtex4 -srl16type=2 --asyncoutwidth=1 +-asyncinwidth=4 +-syncoutwidth=1 -createcdc