From: sithglan Date: Tue, 20 Mar 2007 20:56:19 +0000 (+0000) Subject: changes X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/2268f768ef2c56c06901b433175700a68d371dcc?ds=sidebyside changes --- diff --git a/ethernet/source/pci/pci_user_constants.v b/ethernet/source/pci/pci_user_constants.v index 22ef572..2415dce 100644 --- a/ethernet/source/pci/pci_user_constants.v +++ b/ethernet/source/pci/pci_user_constants.v @@ -39,7 +39,10 @@ // CVS Revision History // // $Log: pci_user_constants.v,v $ -// Revision 1.1 2007-03-20 17:50:56 sithglan +// Revision 1.2 2007-03-20 20:56:19 sithglan +// changes +// +// Revision 1.1 2007/03/20 17:50:56 sithglan // add shit // // Revision 1.15 2004/08/19 15:27:34 mihad @@ -111,8 +114,8 @@ `define PCIW_ADDR_LENGTH 3 `define PCIR_ADDR_LENGTH 3 -//`define FPGA -//`define XILINX +`define FPGA +`define XILINX `define WB_RAM_DONT_SHARE `define PCI_RAM_DONT_SHARE @@ -137,8 +140,8 @@ // these two defines allow user to select active high or low output enables on PCI bus signals, depending on // output buffers instantiated. Xilinx FPGAs use active low output enables. -`define ACTIVE_LOW_OE -//`define ACTIVE_HIGH_OE +// `define ACTIVE_LOW_OE +`define ACTIVE_HIGH_OE // HOST/GUEST implementation selection - see design document and specification for description of each implementation // only one can be defined at same time diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 0541222..c54fa40 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -204,17 +204,17 @@ signal wbm_adr_o : std_logic_vector(31 downto 0); BEGIN -PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; -PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z'; -PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z'; -PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z'; -PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z'; -PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z'; -PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z'; -PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z'; +PCI_RSTn <= not pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; +PCI_INTAn <= not pci_inta_o when (pci_inta_oe_o = '1') else 'Z'; +PCI_REQn <= not pci_req_o when (pci_req_oe_o = '1') else 'Z'; +PCI_FRAMEn <= not pci_frame_o when (pci_frame_oe_o = '1') else 'Z'; +PCI_IRDYn <= not pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z'; +PCI_DEVSELn <= not pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z'; +PCI_TRDYn <= not pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z'; +PCI_STOPn <= not pci_stop_o when (pci_stop_oe_o = '1') else 'Z'; PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z'; -PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z'; -PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z'; +PCI_PERRn <= not pci_perr_o when (pci_perr_oe_o = '1') else 'Z'; +PCI_SERRn <= not pci_serr_o when (pci_serr_oe_o = '1') else 'Z'; MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z'; BLA1: FOR i in 31 downto 0 generate @@ -258,16 +258,16 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( wbm_rty_i => '0', wbm_err_i => wb_err_o, pci_clk_i => PCI_CLOCK, - pci_rst_i => PCI_RSTn, + pci_rst_i => not PCI_RSTn, pci_rst_o => pci_rst_o , pci_rst_oe_o => pci_rst_oe_o, - pci_inta_i => PCI_INTAn, + pci_inta_i => not PCI_INTAn, pci_inta_o => pci_inta_o, pci_inta_oe_o => pci_inta_oe_o, pci_req_o => pci_req_o, pci_req_oe_o => pci_req_oe_o, - pci_gnt_i => PCI_GNTn, - pci_frame_i => PCI_FRAMEn, + pci_gnt_i => not PCI_GNTn, + pci_frame_i => not PCI_FRAMEn, pci_frame_o => pci_frame_o, pci_frame_oe_o => pci_frame_oe_o, pci_irdy_oe_o => pci_irdy_oe_o, @@ -276,23 +276,23 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( pci_stop_oe_o => pci_stop_oe_o, pci_ad_oe_o => pci_ad_oe_o, pci_cbe_oe_o => pci_cbe_oe_o, - pci_irdy_i => PCI_IRDYn, + pci_irdy_i => not PCI_IRDYn, pci_irdy_o => pci_irdy_o, pci_idsel_i => PCI_IDSEL, - pci_devsel_i => PCI_DEVSELn, + pci_devsel_i => not PCI_DEVSELn, pci_devsel_o => pci_devsel_o, - pci_trdy_i => PCI_TRDYn, + pci_trdy_i => not PCI_TRDYn, pci_trdy_o => pci_trdy_o, - pci_stop_i => PCI_STOPn, + pci_stop_i => not PCI_STOPn, pci_stop_o => pci_stop_o, pci_ad_i => PCI_AD, pci_ad_o => pci_ad_o, - pci_cbe_i => PCI_CBEn, + pci_cbe_i => not PCI_CBEn, pci_cbe_o => pci_cbe_o, pci_par_i => PCI_PAR, pci_par_o => pci_par_o, pci_par_oe_o => pci_par_oe_o, - pci_perr_i => PCI_PERRn, + pci_perr_i => not PCI_PERRn, pci_perr_o => pci_perr_o, pci_perr_oe_o => pci_perr_oe_o, pci_serr_o => pci_serr_o,