From: michael Date: Sat, 10 Mar 2007 12:40:33 +0000 (+0000) Subject: loopback X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/257c0fc1ab9ee166000bf5080191b0e62a507dc0 loopback --- diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd index 3036632..215b980 100644 --- a/dhwk/source/top.vhd +++ b/dhwk/source/top.vhd @@ -16,8 +16,8 @@ entity dhwk is PCI_IDSEL : In std_logic; PCI_IRDYn : In std_logic; PCI_RSTn : In std_logic; - SERIAL_IN : In std_logic; - SPC_RDY_IN : In std_logic; +-- SERIAL_IN : In std_logic; +-- SPC_RDY_IN : In std_logic; TAST_RESn : In std_logic; TAST_SETn : In std_logic; PCI_AD : InOut std_logic_vector (31 downto 0); @@ -28,8 +28,8 @@ entity dhwk is PCI_SERRn : Out std_logic; PCI_STOPn : Out std_logic; PCI_TRDYn : Out std_logic; - SERIAL_OUT : Out std_logic; - SPC_RDY_OUT : Out std_logic; +-- SERIAL_OUT : Out std_logic; +-- SPC_RDY_OUT : Out std_logic; TB_IDSEL : Out std_logic; TB_nDEVSEL : Out std_logic; TB_nINTA : Out std_logic ); @@ -82,6 +82,10 @@ architecture SCHEMATIC of dhwk is signal S_FIFO_RESETn : std_logic; signal S_FIFO_RTn : std_logic; signal S_FIFO_WRITEn : std_logic; + signal SERIAL_IN : std_logic; + signal SPC_RDY_IN : std_logic; + signal SERIAL_OUT : std_logic; + signal SPC_RDY_OUT : std_logic; component MESS_1_TB Port ( DEVSELn : In std_logic; @@ -213,6 +217,8 @@ component fifo_generator_v3_2 end component; begin + SERIAL_IN <= SERIAL_OUT; + SPC_RDY_IN <= SPC_RDY_OUT; I19 : MESS_1_TB Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,