From: michael Date: Tue, 20 Mar 2007 23:34:59 +0000 (+0000) Subject: clock X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/2c4b2f251e1176f85357fd1f35d46ba9347b0631?ds=sidebyside clock --- diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index d181c52..184e744 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -277,6 +277,8 @@ end generate; wb_adr_i <= wbm_adr_o (11 downto 2); +wb_clk_i <= PCI_CLOCK; + Inst_pci_bridge32: pci_bridge32 PORT MAP( wb_clk_i => wb_clk_i , wb_rst_i => '0',