From: sithglan Date: Tue, 20 Mar 2007 22:39:24 +0000 (+0000) Subject: WISHBONE B3 X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/361ec26f7bd0c6ecd99a7eac5112d4c61205b82f?ds=sidebyside WISHBONE B3 --- diff --git a/ethernet/source/ethernet/eth_defines.v b/ethernet/source/ethernet/eth_defines.v index aaad999..685b5f5 100644 --- a/ethernet/source/ethernet/eth_defines.v +++ b/ethernet/source/ethernet/eth_defines.v @@ -41,7 +41,10 @@ // CVS Revision History // // $Log: eth_defines.v,v $ -// Revision 1.2 2007-03-20 22:17:38 sithglan +// Revision 1.3 2007-03-20 22:39:24 sithglan +// WISHBONE B3 +// +// Revision 1.2 2007/03/20 22:17:38 sithglan // += use xilinx block ram for ethernet // // Revision 1.1 2007/03/19 16:44:04 sithglan @@ -337,8 +340,7 @@ `define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH // WISHBONE interface is Revision B3 compliant (uncomment when needed) -//`define ETH_WISHBONE_B3 - +`define ETH_WISHBONE_B3 // Following defines are needed when eth_cop.v is used. Otherwise they may be deleted. `define ETH_BASE 32'hd0000000 diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 0541222..68188ac 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -72,6 +72,8 @@ PORT( mdc_pad_o : OUT std_logic; md_pad_o : OUT std_logic; md_padoe_o : OUT std_logic; + m_wb_cti_o : OUT std_logic_vector(2 downto 0); + m_wb_bte_o : OUT std_logic_vector(1 downto 0); int_o : OUT std_logic ); END COMPONENT; @@ -202,6 +204,9 @@ signal md_padoe_o : std_logic; signal int_o : std_logic; signal wbm_adr_o : std_logic_vector(31 downto 0); +signal m_wb_cti_o : std_logic_vector(2 downto 0); +signal m_wb_bte_o : std_logic_vector(1 downto 0); + BEGIN PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; @@ -240,8 +245,8 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( wbs_cyc_i => m_wb_cyc_o, wbs_stb_i => m_wb_stb_o, wbs_we_i => m_wb_we_o, - wbs_cti_i => (others => '0'), - wbs_bte_i => (others => '0'), + wbs_cti_i => m_wb_cti_o, + wbs_bte_i => m_wb_bte_o, wbs_ack_o => m_wb_ack_i, -- wbs_rty_o => , wbs_err_o => m_wb_err_i, @@ -334,6 +339,8 @@ Inst_eth_top: eth_top PORT MAP( md_pad_i => MD_PAD_IO, md_pad_o => md_pad_o, md_padoe_o => md_padoe_o, + m_wb_cti_o => m_wb_cti_o, + m_wb_bte_o => m_wb_bte_o, int_o => int_o );