From: sithglan Date: Sun, 11 Mar 2007 11:59:56 +0000 (+0000) Subject: get rid of vergleich X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/3c76f814e51b2574a0cdc5dc3dc5710f31fbc443?hp=7c54167d1f3a37b18f51ebe28d8820f04438bbc4 get rid of vergleich --- diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj index 9b412ff..33b048c 100644 --- a/dhwk/dhwk.prj +++ b/dhwk/dhwk.prj @@ -28,7 +28,3 @@ vhdl work "source/pci/synplify.vhd" vhdl work "source/pci/top.vhd" vhdl work "source/pci/user_io.vhd" vhdl work "source/pci/ven_rev_id.vhd" -vhdl work "source/pci/verg_2.vhd" -vhdl work "source/pci/verg_4.vhd" -vhdl work "source/pci/verg_8.vhd" -vhdl work "source/pci/vergleich.vhd" diff --git a/dhwk/source/pci/pci_interface.vhd b/dhwk/source/pci/pci_interface.vhd index 722cce6..d15f9da 100644 --- a/dhwk/source/pci/pci_interface.vhd +++ b/dhwk/source/pci/pci_interface.vhd @@ -109,12 +109,6 @@ architecture SCHEMATIC of PCI_INTERFACE is SERR : Out std_logic ); end component; - component VERGLEICH - Port ( IN_A : In std_logic_vector (31 downto 0); - IN_B : In std_logic_vector (31 downto 0); - GLEICH_OUT : Out std_logic ); - end component; - component IO_MUX_REG Port ( CONFIG_DATA : In std_logic_vector (31 downto 0); LOAD_ADDR_REG : In std_logic; @@ -189,10 +183,6 @@ begin SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8), PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR ); - I4 : VERGLEICH - Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0), - IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - GLEICH_OUT=>MY_ADDR ); I2 : IO_MUX_REG Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0), LOAD_ADDR_REG=>LAR, @@ -222,4 +212,17 @@ begin CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0), CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) ); + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + MY_ADDR <= '0'; + + elsif (rising_edge(PCI_CLOCK)) then + if (CONF_DATA_10H(31 downto 2) = ADDR_REG_DUMMY(31 downto 2)) then + MY_ADDR <= '1'; + else + MY_ADDR <= '0'; + end if; + end if; + end process; end SCHEMATIC; diff --git a/dhwk/source/pci/verg_2.vhd b/dhwk/source/pci/verg_2.vhd deleted file mode 100644 index bbea0ea..0000000 --- a/dhwk/source/pci/verg_2.vhd +++ /dev/null @@ -1,33 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: VERG_2.VHD - -library ieee; -use ieee.std_logic_1164.all; - -entity VERG_2 is - port - ( - IN_A :in std_logic_vector(1 downto 0); - IN_B :in std_logic_vector(1 downto 0); - GLEICH :out std_logic - ); -end entity VERG_2; - -architecture VERG_2_DESIGN of VERG_2 is - -begin - - process (IN_A,IN_B) - begin - - if IN_A = IN_B then - GLEICH <= '1'; - else - GLEICH <= '0'; - end if; - -end process; - -end architecture VERG_2_DESIGN; diff --git a/dhwk/source/pci/verg_4.vhd b/dhwk/source/pci/verg_4.vhd deleted file mode 100644 index 02edc30..0000000 --- a/dhwk/source/pci/verg_4.vhd +++ /dev/null @@ -1,33 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: VERG_4.VHD - -library ieee; -use ieee.std_logic_1164.all; - -entity VERG_4 is - port - ( - IN_A :in std_logic_vector(3 downto 0); - IN_B :in std_logic_vector(3 downto 0); - GLEICH :out std_logic - ); -end entity VERG_4; - -architecture VERG_4_DESIGN of VERG_4 is - -begin - - process (IN_A,IN_B) - begin - - if IN_A = IN_B then - GLEICH <= '1'; - else - GLEICH <= '0'; - end if; - end process; - -end architecture VERG_4_DESIGN; - diff --git a/dhwk/source/pci/verg_8.vhd b/dhwk/source/pci/verg_8.vhd deleted file mode 100644 index ea7a499..0000000 --- a/dhwk/source/pci/verg_8.vhd +++ /dev/null @@ -1,27 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: VERG_8.VHD - -library ieee; -use ieee.std_logic_1164.all; - -entity VERG_8 is - port - ( - GLEICH :in std_logic_vector(7 downto 0); - GLEICH_OUT :out std_logic - ); - -end entity VERG_8; - -architecture VERG_8_DESIGN of VERG_8 is - -begin - - -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte - - -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0'; - GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0'; - -end architecture VERG_8_DESIGN; diff --git a/dhwk/source/pci/vergleich.vhd b/dhwk/source/pci/vergleich.vhd deleted file mode 100644 index 55aacd3..0000000 --- a/dhwk/source/pci/vergleich.vhd +++ /dev/null @@ -1,69 +0,0 @@ --- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007 - -LIBRARY ieee; - -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - - -entity VERGLEICH is - Port ( IN_A : In std_logic_vector (31 downto 0); - IN_B : In std_logic_vector (31 downto 0); - GLEICH_OUT : Out std_logic ); -end VERGLEICH; - -architecture SCHEMATIC of VERGLEICH is - - SIGNAL gnd : std_logic := '0'; - SIGNAL vcc : std_logic := '1'; - - signal GLEICH : std_logic_vector (7 downto 0); - - component VERG_2 - Port ( IN_A : In std_logic_vector (1 downto 0); - IN_B : In std_logic_vector (1 downto 0); - GLEICH : Out std_logic ); - end component; - - component VERG_8 - Port ( GLEICH : In std_logic_vector (7 downto 0); - GLEICH_OUT : Out std_logic ); - end component; - - component VERG_4 - Port ( IN_A : In std_logic_vector (3 downto 0); - IN_B : In std_logic_vector (3 downto 0); - GLEICH : Out std_logic ); - end component; - -begin - - I11 : VERG_2 - Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2), - IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) ); - I9 : VERG_8 - Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0), - GLEICH_OUT=>GLEICH_OUT ); - I8 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28), - IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) ); - I7 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24), - IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) ); - I6 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20), - IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) ); - I5 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16), - IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) ); - I4 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12), - IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) ); - I3 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8), - IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) ); - I2 : VERG_4 - Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4), - IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) ); - -end SCHEMATIC;