From: sithglan <sithglan>
Date: Wed, 21 Mar 2007 12:13:26 +0000 (+0000)
Subject: do it right
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/3f7aa67598761f54ca4768919ad8e714c73c1190?hp=23944ea1558725bf7722ae42f0e5b52ed958eded

do it right
---

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index d1a47da..45d3f29 100644
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -220,7 +220,6 @@ signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
-signal wb_stb_i_helper : std_logic_vector(31 downto 0);
 
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
@@ -253,10 +252,8 @@ BLA2: FOR i in 3 downto 0 generate
 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 end generate;
 
-wb_adr_i <= wbm_adr_o (11 downto 2);
-
-wb_stb_i_helper(32 downto 8) <= (others => '0');
-wb_stb_i_helper(7 downto 0) <= wbm_adr_o (7 downto 0);
+wb_adr_i(11 downto 2) <= (others => '0');
+wb_adr_i <= wbm_adr_o (7 downto 2);
 
 wb_clk_i <= PCI_CLOCK;
 
@@ -350,7 +347,7 @@ Inst_eth_top: eth_top PORT MAP(
         wb_sel_i   => wb_sel_i  ,
         wb_we_i    => wb_we_i   ,
         wb_cyc_i   => wb_cyc_i  ,
-        wb_stb_i   => wb_stb_i_helper  ,
+        wb_stb_i   => wb_stb_i,
         wb_ack_o   => wb_ack_o  ,
         wb_err_o   => wb_err_o  ,
         m_wb_adr_o => m_wb_adr_o,