From: michael Date: Wed, 21 Mar 2007 14:01:16 +0000 (+0000) Subject: a bit better X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/675f45d062971a8e9a17be7aa2f19b102d60c7b0?ds=sidebyside a bit better --- diff --git a/ethernet/phydcm.xaw b/ethernet/phydcm.xaw index 262cfc5..573e496 100644 --- a/ethernet/phydcm.xaw +++ b/ethernet/phydcm.xaw @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.4e -$9cx73=(`fgn#`glh`go+Wg`olnxxb`j/scdc`bt|fdn#hzgeslfp*bde'rj{<5?4:2-437<9;1:=55>6&j;4=6538R:7?:42/046>45:282:6=?.2206>54?23%=#>=i69BVFNPAS;<7L\XZ^MMH\YDIZIJHD@H_BNH5==FZ^PTCCBV_BNHMKYBP]OYBLB>5:CQS_YHFESTOAEFN^TBHPC6j2KY[WQ@NM[\@FKX[^C_OEGAG^AOO466:CQS_YHFESTHI\PFMKSBIIW9<1J^ZTPOONZ[CDXMQ^N^COC139BVR\XGGFRSD@\T^LVI`=FZ^PTCCBV_QO@@43GPRVIGGO[ITXRF540GPRVLGCZZVPD:8ER\XXHX_h6OXZ^QZJQNSGFF?7OA[H59AQCA33JF@<55LLJ2\FP@b3JF@8178GIM>8<1H@FJYc:AOOAPXL@\BHH;4CMIEF==DDBLISD@:;BNHB]>4CMIJJZOE]OMTEC][f:AOOLHXAK_MKRAZT99@HNOIW@Dh7NBDIO]SAWOHLl1H@FGA_RP@[Q_WM880OAE@UU]SLDUBWZBBJYm4CMI\B@CCJHI@56M@MLKWP@B03JXNMYKK3:F@I==CKDUBB^Zk;EGPO@QXIM@^_Y?=;EDP[CTBY\OEOTQBOEGb?AJKWHDOSKV>2:FOHZ@UMX_NBNWPMNFF1>BT[LD:96JZTX]@]FJBWJEY^HM[INL4?AYQIE_N46KWTDPMEIg@BMMHJOFQMUG;8BLHX]GC__l5IOTV\QKOS[h1MCXZPV@NVA4=N=2CIYKI7;HLWAWHFD8;0FDZ[ES]JJUSSW]S[In5EIUVFVZVL:YAh7GG[TDP\RDJRM?1GCLJJD79OKFMBLh1GCNEJD^MVP6=KG^90AETm;L]BJAYCWZ^Y;6CPV@NVA2=IM]]D^F:4NNLF5>I?3FLOH_M_Ec9SLDUBWZBBJY74PHLKEVDR[h1[ECG\GOFF@==WAG]BHYF7;QPJIQ_WM8:0\_A__QKMMVGD\@\N96^\CMI5?UUCGGO?7]]JN99SWLHDLLI87_][6:PPPZOIj2YBKHV[ESLBH3=TAGMGIn5\T@PWQUYPI@^=7^ZNTTQ26>U^[]OFS^WACIPLJJST;2^D\95[RTG;?PUBWK_MK45ZSD]AQCAT=2\BIZ?m;YCT[SCU[@EE=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB?6V\T79[`gYNl8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`:;Z294X3>hm1;03<3`|f1;1=6`72;68 =6=?l1v_9=5848;3?74::li=70_9=5848;3?74::li=7=1=9:88jo?521:5b>pS?j0;6<4>:`yP0176?>o1i;54?:187>d}#m32=7)?48f:&4`?b5;06?!712?<0(<95759'5=<43-;26;:4$0c915=#9k09?6*;2;48 7`=?2.8:7o4$259=>"4i3?;7)=i:c9'05<3m2.?=78;;%64>21<,=n1m6*;8;7e?!2f281/:?46;%44>4=#?<0><6*8a;5a?!762j1/=k4;9:&6f?4<,;1<7*9a;:0?!0d2>307d8i:18'2d5+6884=>=n>m0;6)8n:918 3?=?010e9l50;&5e?>43-<26:74;n06>5<#>h03?6*9c;5:?!7c2;>0(54o3c94?"1i32876a=e;29 3g=0:10c?l50;&5e?>432e9o7>5$7c9<6=30(=h=m0;6)8n:918 3e=?010c;k50;&5e?>432wi?n4?:383>5}#>k0>;6g:6;29 3g=0:1/:n489:9l20<72-0e8850;&5e?>43-5<#>h03?6*9c;5:?>{e;<0;6?4?:1y'2g<5<2c>:7>5$7c9<6=#>j0<565`6483>!0f2190(;m57898yv5e2909w0:9:2;896e=><1/=n45<6s4>=6:?4$61913=z{;<1<70>:6s|3583>7}:63<5;75?xu2m3:1=v3;6;7g?!142??0q~=j:18285d2<<0(:=5579~w6>=83;p1>;5649'36<1=2wx?i4?:1y'36<1=2wx>54?:1y'36<1=2wvb?950;3xyk4?290:wp`=9;295~{i:h0;6{|l1`?6=9rwe>h4?:0y~j7`=83;pqc=?:182x{zuIJHw>l5165;b5dfuIJIw=sO@Qy~DE \ No newline at end of file +$97x73=(`fgn#`glh`go+Wg`olnxxb`j/scdc`bt|fdn#hzgeslfp*bde'rj{<5?4:2-437<9;1:=55>6&j;4=6538R:7?:42/046>45:282:6=?.2206>54?23%=#>=i69BVFNPAS;<7L\XZ^MMH\YDIZIJHD@H_BNH5==FZ^PTCCBV_BNHMKYBP]OYBLB>5:CQS_YHFESTOAEFN^TBHPC6j2KY[WQ@NM[\@FKX[^C_OEGAG^AOO466:CQS_YHFESTHI\PFMKSBIIW9<1J^ZTPOONZ[CDXMQ^N^COC139BVR\XGGFRSD@\T^LVI`=FZ^PTCCBV_QO@@43GPRVIGGO[ITXRF540GPRVLGCZZVPD:8ER\XXHX_h6OXZ^QZJQNSGFF?7OA[H59AQCA33JF@<55LLJ2\FP@b3JF@8178GIM>8<1H@FJYc:AOOAPXL@\BHH;4CMIEF==DDBLISD@:;BNHB]>BDEVCE_Yj4DDQHARYFLC_XX<<4DGQ\BWCV]LDHURC@DDc8@IJXIGNTJU?=;ENO[CTBY\OEOTQBOEG6?AUTMG;>7I[[Y^AZGICXKFXYINZFOO58@ZPFD\Oj7KOLTNPZ[O@23OKG_H74FC]PKPTDMj1MIHJMABI\FP@>3OCESX@FTRc8BJSSW\DBX^o4FNWW[SGK]L;0E55FNUGQJDJ692@BXYK]_HLSQQYSQYOh7GG[TDP\TN4WCj1AEYZJR^TBHPC13EEJHHJ9;MM@O@Bf3EEHGHJPOTV0?IIP;2GCVo5B_@LG[AYT\[=0ARXNLTG4?KCS_FX@86@@ND38K==HNMNYO]Km;QJBW@YT@@L_56^FNICPFPUf3YCEE^IADDF;?UOI_@N_D55_RHOW]UC682ZYC]Q_IOKPEFRN^L?0\^MCK79SWAIIM=1[_H@7;QQJJFBBK:1Y_Y84RRV\MKd<[@MNTYK]N@N5?VOIOEOh7^ZNRUWS[RGN\?1XXLZZS008W\USMDUXUCMGRNLLQV5<\FZ?7Y\ZE99VW@YE]OM27X]J_CWECV3<^@O\=o5WAV]UAWUNGG;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@90T^Z9;Yfa[Lb682RoaRCnjnpUawungg;;7Ujb_LkmkwPbzzcdb85T0;2^1>]72>W?7l|xz29gghd<~lxxeb`/1/27?sncd8:0tn=|1423)ca3=?'?qMN379CD}6=N3<1=v];1;:3>=4=9:88jo?521:5b~h0k3;0b:j54:&4f?1>3tY?<76?:9095644nk;1>=olb:Q63?>72181=><=k:2:Q63?>72181=><=6=0;0:??=ib0814=0a3k=86=4?:28;!c=081/>=473:&15?>33-896:o4$6:9`>d3;3:1=>4?:1y'23<3:2.m6?k4$0292c=#9;0996*>3;06?!732;30(<;5249'53<192.:;78i;%3;>6=#900>j6*>a;6`?!7e2;90(>h56:&1b?1<,:<1m6*<7;;8 6g=05<,:o19k5+45846>"3i3k0(9;55`9'02<2i2.?579;;%6a>0=#?6*;f;7a?!372"2=320e>750;&51?1b3-<<6::4;h13>5<#><0o1k3:1(;;57d9'22<0<21b:l4?:%46>2c<,?>1;954i7`94?"1=3=n7)8;:668?l0?290/:848e:&50?1332c?47>5$7793`=#>=0<865`2483>!022>o0(;95759'5a<5<2.:i7:j;:m1`?6=,??1;h54o3;94?"1=3=n76a=a;29 33=?l10c?k50;&51?1b32e9n7>5$7793`=i4:3:1(;;57d9'22<0<2.:h7<;;:m07?6=,??1;h54o6394?"1=3=m7)8<:668?j3?290/:848e:&53?1332e=57>5$7793`=0e8<50;&51?1b3-<<6::4;n43>5<#><0{e;<0;6?4?:1y'23<5<2c>>7>5$7793`=#>>0<865`6183>!022>o0(;957598yv5e290:w0:<:2;8 3c==;1v>?50;0x915=;916>:490:&2g?4?3ty=h7>51z?77?0d3-5<5s4>86?;4=35917=z{:>1<7>6s|5883>4}:<:0>46*9e;43?xu403:1=v3<5;43?!0b2?:0q~<7:183!0b2?:0qp`=6;295~{i:>0;6{|l1e?6=9rwe>o4?:0y~j7e=83;pqc85927;7415uIJIw=sO@Qy~DE \ No newline at end of file diff --git a/ethernet/source/phydcm.vhd b/ethernet/source/phydcm.vhd index efec74a..a5db448 100644 --- a/ethernet/source/phydcm.vhd +++ b/ethernet/source/phydcm.vhd @@ -7,7 +7,7 @@ -- \ \ \/ Version : 9.1.02i -- \ \ Application : xaw2vhdl -- / / Filename : phydcm.vhd --- /___/ /\ Timestamp : 03/21/2007 14:47:39 +-- /___/ /\ Timestamp : 03/21/2007 14:56:33 -- \ \ / \ -- \___\/\___\ -- @@ -26,30 +26,23 @@ library UNISIM; use UNISIM.Vcomponents.ALL; entity phydcm is - port ( CLKIN_IN : in std_logic; - RST_IN : in std_logic; - CLKFX_OUT : out std_logic; - CLKIN_IBUFG_OUT : out std_logic; - CLK0_OUT : out std_logic; - LOCKED_OUT : out std_logic); + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); end phydcm; architecture BEHAVIORAL of phydcm is - signal CLKFB_IN : std_logic; - signal CLKFX_BUF : std_logic; - signal CLKIN_IBUFG : std_logic; - signal CLK0_BUF : std_logic; - signal GND_BIT : std_logic; + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; component BUFG port ( I : in std_logic; O : out std_logic); end component; - component IBUFG - port ( I : in std_logic; - O : out std_logic); - end component; - -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns component DCM @@ -91,16 +84,11 @@ architecture BEHAVIORAL of phydcm is begin GND_BIT <= '0'; - CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); - CLKIN_IBUFG_INST : IBUFG - port map (I=>CLKIN_IN, - O=>CLKIN_IBUFG); - CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); @@ -121,7 +109,7 @@ begin PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, - CLKIN=>CLKIN_IBUFG, + CLKIN=>CLKIN_IN, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 480de0a..1617eee 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -175,7 +175,6 @@ component phydcm is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; - CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end component; @@ -406,10 +405,9 @@ eth_dcm : phydcm port map ( CLKIN_IN => PCI_CLOCK, RST_IN => not PCI_RSTn, - CLKFX_OUT => PHY_CLOCK --- CLKIN_IBUFG_OUT --- CLK0_OUT --- LOCKED_OUT + CLKFX_OUT => PHY_CLOCK, + CLK0_OUT => open, + LOCKED_OUT => open ); end architecture ethernet_arch;