From: michael Date: Wed, 21 Mar 2007 13:18:23 +0000 (+0000) Subject: clock X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/7a6a1ff70fc526bd7f7feacdf2f25ee77f779260 clock --- diff --git a/ethernet/ethernet.ucf b/ethernet/ethernet.ucf index 157a5e3..b62ae07 100644 --- a/ethernet/ethernet.ucf +++ b/ethernet/ethernet.ucf @@ -74,4 +74,6 @@ NET "MCRS_PAD_I" LOC = "U3" | IOSTANDARD = LVCMOS33; NET "MD_PAD_IO" LOC = "Y1" | IOSTANDARD = LVCMOS33; NET "MDC_PAD_O" LOC = "U2" | IOSTANDARD = LVCMOS33; +NET "PHY_CLOCK" LOC = "L5" | IOSTANDARD = LVCMOS33; + NET "LED_2" LOC = "AB5" | IOSTANDARD = LVTTL | DRIVE = 24 ; diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index c031ae6..611e9c0 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -32,6 +32,8 @@ PORT( MD_PAD_IO : INOUT std_logic; MDC_PAD_O : OUT std_logic; + PHY_CLOCK : OUT std_logic; + LED_2 : OUT std_logic ); end ethernet; @@ -256,6 +258,7 @@ wb_adr_i(11 downto 8) <= (others => '0'); wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2); wb_clk_i <= PCI_CLOCK; +PHY_CLOCK <= PCI_CLOCK; data(31 downto 0) <= wbm_adr_o; data(40 downto 33) <= wbm_adr_o (7 downto 0);