From: sithglan Date: Sun, 11 Mar 2007 11:16:52 +0000 (+0000) Subject: even more consolidation X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/816293e0b569a4cb30f94f8f9dacfb721039ed1d?ds=sidebyside even more consolidation --- diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj index 8d0f4f7..dba1b3b 100644 --- a/dhwk/dhwk.prj +++ b/dhwk/dhwk.prj @@ -3,7 +3,6 @@ vhdl work "source/ser_par_con.vhd" vhdl work "source/pci/address_register.vhd" vhdl work "source/pci/comm_dec.vhd" vhdl work "source/pci/comm_fsm.vhd" -vhdl work "source/pci/config_04h.vhd" vhdl work "source/pci/config_rd_0.vhd" vhdl work "source/pci/config_space_header.vhd" vhdl work "source/pci/config_wr_0.vhd" diff --git a/dhwk/source/pci/config_04h.vhd b/dhwk/source/pci/config_04h.vhd deleted file mode 100644 index 5e26083..0000000 --- a/dhwk/source/pci/config_04h.vhd +++ /dev/null @@ -1,113 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_04H.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_04H is - port - ( - PCI_CLOCK :in std_logic; - PCI_RSTn :in std_logic; - SERR :in std_logic; - PERR :in std_logic; - AD_REG :in std_logic_vector(31 downto 0); - CBE_REGn :in std_logic_vector( 3 downto 0); - CONF_WR_04H :in std_logic; - CONF_DATA_04H :out std_logic_vector(31 downto 0) - ); -end entity CONFIG_04H; - -architecture CONFIG_04H_DESIGN of CONFIG_04H is - - signal CONF_STATUS :std_logic_vector(31 downto 16); - signal CONF_COMMAND :std_logic_vector(15 downto 0); - -begin - - --******************************************************************* - --************* PCI Configuration Space Header "STATUS" ************* - --******************************************************************* - - CONF_STATUS(20 downto 16) <= "00000";-- Reserved - CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz - CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O" - CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back - CONF_STATUS(24 ) <= '0';-- Master : - --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL" - CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL" - --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL" - --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved - CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort - CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort - CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort - --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR - --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR - - process (PCI_CLOCK,PCI_RSTn) - begin - if PCI_RSTn = '0' then - CONF_STATUS(30) <= '0'; - CONF_STATUS(31) <= '0'; - - elsif (rising_edge(PCI_CLOCK)) then - if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then - CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); - CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); - - else - CONF_STATUS(30) <= SERR or CONF_STATUS(30); - CONF_STATUS(31) <= PERR or CONF_STATUS(31); - - end if; - end if; -end process; - - --******************************************************************* - --*********** PCI Configuration Space Header "COMMAND" ************** - --******************************************************************* - --- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ??? --- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ??? --- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus --- CONF_COMMAND( 3) <= '0';-- Special Cycle ??? --- CONF_COMMAND( 4) <= '0';-- Master ??? --- CONF_COMMAND( 5) <= '0';-- VGA ??? --- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable -CONF_COMMAND( 7) <= '0';-- address/data stepping ??? --- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn" --- CONF_COMMAND( 9) <= '0';-- fast back-to-back --- CONF_COMMAND(10) <= '0';-- Reserved --- CONF_COMMAND(11) <= '0';-- Reserved --- CONF_COMMAND(12) <= '0';-- Reserved --- CONF_COMMAND(13) <= '0';-- Reserved --- CONF_COMMAND(14) <= '0';-- Reserved --- CONF_COMMAND(15) <= '0';-- Reserved - -process (PCI_CLOCK,PCI_RSTn) -begin - if PCI_RSTn = '0' then - CONF_COMMAND(15 downto 8) <= (others =>'0'); - CONF_COMMAND( 6 downto 0) <= (others =>'0'); - - elsif (rising_edge(PCI_CLOCK)) then - - if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then - CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); - else - CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8); - end if; - - if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then - CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0); - else - CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0); - end if; - end if; -end process; - -CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; - -end architecture CONFIG_04H_DESIGN; diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd index 722b931..ca437c0 100644 --- a/dhwk/source/pci/config_space_header.vhd +++ b/dhwk/source/pci/config_space_header.vhd @@ -38,6 +38,9 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0); + signal CONF_STATUS :std_logic_vector(31 downto 16); + signal CONF_COMMAND :std_logic_vector(15 downto 0); + SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; @@ -66,22 +69,10 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is CONF_WR_3CH : Out std_logic ); end component; - component CONFIG_04H - Port ( AD_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - CONF_WR_04H : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - PERR : In std_logic; - SERR : In std_logic; - CONF_DATA_04H : Out std_logic_vector (31 downto 0) ); - end component; - begin CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; - - CONF_DATA_04H <= CONF_DATA_04H_DUMMY; + CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; CONF_MAX_LAT <= X"00"; CONF_MIN_GNT <= X"00"; @@ -106,12 +97,6 @@ begin CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn, TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H, CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH ); - I2 : CONFIG_04H - Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), - CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK, - PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR, - CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) ); process (PCI_CLOCK,PCI_RSTn) begin @@ -165,4 +150,85 @@ begin end if; end if; end process; + + --******************************************************************* + --************* PCI Configuration Space Header "STATUS" ************* + --******************************************************************* + + CONF_STATUS(20 downto 16) <= "00000";-- Reserved + CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz + CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O" + CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back + CONF_STATUS(24 ) <= '0';-- Master : + --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL" + CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL" + --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL" + --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved + CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort + CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort + CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort + --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR + --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR + + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + CONF_STATUS(30) <= '0'; + CONF_STATUS(31) <= '0'; + + elsif (rising_edge(PCI_CLOCK)) then + if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then + CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); + CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); + + else + CONF_STATUS(30) <= SERR or CONF_STATUS(30); + CONF_STATUS(31) <= PERR or CONF_STATUS(31); + + end if; + end if; + end process; + + --******************************************************************* + --*********** PCI Configuration Space Header "COMMAND" ************** + --******************************************************************* + + -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ??? + -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ??? + -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus + -- CONF_COMMAND( 3) <= '0';-- Special Cycle ??? + -- CONF_COMMAND( 4) <= '0';-- Master ??? + -- CONF_COMMAND( 5) <= '0';-- VGA ??? + -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable + CONF_COMMAND( 7) <= '0';-- address/data stepping ??? + -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn" + -- CONF_COMMAND( 9) <= '0';-- fast back-to-back + -- CONF_COMMAND(10) <= '0';-- Reserved + -- CONF_COMMAND(11) <= '0';-- Reserved + -- CONF_COMMAND(12) <= '0';-- Reserved + -- CONF_COMMAND(13) <= '0';-- Reserved + -- CONF_COMMAND(14) <= '0';-- Reserved + -- CONF_COMMAND(15) <= '0';-- Reserved + + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + CONF_COMMAND(15 downto 8) <= (others =>'0'); + CONF_COMMAND( 6 downto 0) <= (others =>'0'); + + elsif (rising_edge(PCI_CLOCK)) then + + if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then + CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); + else + CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8); + end if; + + if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then + CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0); + else + CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0); + end if; + end if; + end process; end SCHEMATIC;