From: sithglan Date: Sun, 11 Feb 2007 21:58:30 +0000 (+0000) Subject: += fifo X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/96e85c4d4bf3ce4b6d1716079373592e6041cdc5 += fifo --- diff --git a/dhwk_old/source/generic_fifo_sc_a.v b/dhwk_old/source/generic_fifo_sc_a.v new file mode 100644 index 0000000..a04727f --- /dev/null +++ b/dhwk_old/source/generic_fifo_sc_a.v @@ -0,0 +1,342 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: generic_fifo_sc_a.v,v 1.1 2007-02-11 21:58:30 sithglan Exp $ +// +// $Date: 2007-02-11 21:58:30 $ +// $Revision: 1.1 $ +// $Author: sithglan $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: generic_fifo_sc_a.v,v $ +// Revision 1.1 2007-02-11 21:58:30 sithglan +// += fifo +// +// Revision 1.1.1.1 2002/09/25 05:42:06 rudi +// Initial Checkin +// +// +// +// +// +// +// +// +// +// +// + +`include "timescale.v" + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + + +module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re, + full, empty, full_r, empty_r, + full_n, empty_n, full_n_r, empty_n_r, + level); + +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (n-1) ) & !re) empty_n_r <= #1 1'b0; + else + if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1; + +always @(posedge clk `SC_FIFO_ASYNC_RESET) + if(!rst) full_n_r <= #1 1'b0; + else + if(clr) full_n_r <= #1 1'b0; + else + if(we & (cnt >= (max_size-n) ) & !re) full_n_r <= #1 1'b1; + else + if(re & (cnt <= (max_size-n+1)) & !we) full_n_r <= #1 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Sanity Check +// + +// synopsys translate_off +always @(posedge clk) + if(we & full) + $display("%m WARNING: Writing while fifo is FULL (%t)",$time); + +always @(posedge clk) + if(re & empty) + $display("%m WARNING: Reading while fifo is EMPTY (%t)",$time); +// synopsys translate_on + +endmodule +