From: michael <michael>
Date: Sat, 10 Feb 2007 19:41:07 +0000 (+0000)
Subject: rename pci_7seg to raggedstone
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/ad16d1e3db67bf7bf820254517c1df11f2db5569?hp=e8e63794ba14cbc0bea39aa83da92bf3b0975a80

rename pci_7seg to raggedstone
source files also moved, so be sure to do a cvs update -dp _without_
modified files!
---

diff --git a/common/xc3s1500.batch b/common/xc3s1500.batch
index b1fcb83..09751c3 100644
--- a/common/xc3s1500.batch
+++ b/common/xc3s1500.batch
@@ -1,6 +1,6 @@
 setmode -bscan 
 setcable -p auto 
 identify
-assignFile -p 3 -file pci_7seg.bit
+assignFile -p 3 -file raggedstone.bit
 program -p 3
 quit
diff --git a/heartbeat/Makefile b/heartbeat/Makefile
index 66afb83..ac41e73 100644
--- a/heartbeat/Makefile
+++ b/heartbeat/Makefile
@@ -5,7 +5,7 @@ XST := $(shell which xst)
 TMP = tmp/
 $(shell mkdir tmp)
 
-PROJECT := pci_7seg
+PROJECT := raggedstone
 
 all: xst ngdbuild map par trace prom final
 
diff --git a/heartbeat/raggedstone.prj b/heartbeat/raggedstone.prj
index e0adeac..4b24f2b 100644
--- a/heartbeat/raggedstone.prj
+++ b/heartbeat/raggedstone.prj
@@ -10,5 +10,5 @@ vhdl work "source/pfs.vhd"
 vhdl work "source/new_pciregs.vhd"
 vhdl work "source/pcipargen.vhd"
 vhdl work "source/new_pci32tlite.vhd"
-vhdl work "source/top_pci_7seg.vhd"
+vhdl work "source/top_raggedstone.vhd"
 vhdl work "source/heartbeat.vhd"
diff --git a/heartbeat/raggedstone.xst b/heartbeat/raggedstone.xst
index 33f30fa..b94c962 100644
--- a/heartbeat/raggedstone.xst
+++ b/heartbeat/raggedstone.xst
@@ -1,15 +1,15 @@
 set -xsthdpdir ./xst
 run
--ifn pci_7seg.prj
+-ifn raggedstone.prj
 -ifmt mixed
--ofn pci_7seg
+-ofn raggedstone
 -ofmt NGC
 -p xc3s1500-4-fg456
--top pci_7seg
+-top raggedstone
 -opt_mode Speed
 -opt_level 1
 -iuc NO
--lso pci_7seg.lso
+-lso raggedstone.lso
 -keep_hierarchy NO
 -glob_opt AllClockNets
 -rtlview Yes
diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 73fefb1..2834959 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -38,7 +38,7 @@ use ieee.std_logic_unsigned.all;
 --|									ENTITY   									|
 --+-----------------------------------------------------------------------------+
 
-entity pci_7seg is
+entity raggedstone is
 port (
 
     -- General 
@@ -65,14 +65,14 @@ port (
 	LED_ALIVE : out std_logic
 
 );
-end pci_7seg;
+end raggedstone;
 
 
 --+-----------------------------------------------------------------------------+
 --|									ARCHITECTURE								|
 --+-----------------------------------------------------------------------------+
 
-architecture pci_7seg_arch of pci_7seg is
+architecture raggedstone_arch of raggedstone is
 
 
 --+-----------------------------------------------------------------------------+
@@ -194,4 +194,4 @@ port map(
 	led_o => LED_ALIVE
 );
 
-end pci_7seg_arch;
+end raggedstone_arch;