From: michael <michael>
Date: Sat, 10 Mar 2007 13:36:55 +0000 (+0000)
Subject: ?
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/bba7a6d51635a1cb7d31bdfc03b1a66ee9df336b?hp=56f1d0d6d7ce34b93faf0fe935bd215897a1c58a

?
---

diff --git a/dhwk/dhwk.ucf b/dhwk/dhwk.ucf
index 9a04690..f147e9e 100644
--- a/dhwk/dhwk.ucf
+++ b/dhwk/dhwk.ucf
@@ -57,3 +57,9 @@ NET "PCI_SERRn"  LOC = "B12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_STOPn"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_TRDYn"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "TAST_RESn"  LOC = "AA3"  | IOSTANDARD = LVTTL | PULLUP ;
+NET "TAST_SETn"  LOC = "Y4"   | IOSTANDARD = LVTTL | PULLUP ;
+NET "LED_2"  LOC = "AB5"  | IOSTANDARD = LVTTL | DRIVE = 24 ;
+NET "LED_3"  LOC = "AA5"  | IOSTANDARD = LVTTL | DRIVE = 24 ;
+NET "LED_4"  LOC = "AA4"  | IOSTANDARD = LVTTL | DRIVE = 24 ;
+NET "LED_5"  LOC = "AB4"  | IOSTANDARD = LVTTL | DRIVE = 24 ;
diff --git a/dhwk/source/INTERRUPT.vhd b/dhwk/source/INTERRUPT.vhd
index 00048ba..65d89e1 100644
--- a/dhwk/source/INTERRUPT.vhd
+++ b/dhwk/source/INTERRUPT.vhd
@@ -121,15 +121,15 @@ begin
     end if;
 	end process;
 
-	SIG_PROPAGATE_INT <= SIG_TAST_Q 
-            OR (REG(0) AND INT_MASKE(0)) 
-            OR (REG(1) AND INT_MASKE(1))
-            OR (REG(2) AND INT_MASKE(2))
-            OR (REG(3) AND INT_MASKE(3))
-            OR (REG(4) AND INT_MASKE(4))
-            OR (REG(5) AND INT_MASKE(5))
-            OR (REG(6) AND INT_MASKE(6))
-            OR (REG(7) AND INT_MASKE(7));
+	SIG_PROPAGATE_INT <= SIG_TAST_Q
+            OR (REG(0) AND not INT_MASKE(0)) 
+            OR (REG(1) AND not INT_MASKE(1))
+            OR (REG(2) AND not INT_MASKE(2))
+            OR (REG(3) AND not INT_MASKE(3))
+            OR (REG(4) AND not INT_MASKE(4))
+            OR (REG(5) AND not INT_MASKE(5))
+            OR (REG(6) AND not INT_MASKE(6))
+            OR (REG(7) AND not INT_MASKE(7));
 
 	process (PCI_CLOCK)
 	begin
@@ -140,7 +140,7 @@ begin
 
 
    	  INTAn	<= not SIG_PROPAGATE_INT_SECOND;
-    	PCI_INTAn	<= '1'	when SIG_PROPAGATE_INT_SECOND = '0'	else	'Z';
+    	PCI_INTAn	<= '0'	when SIG_PROPAGATE_INT_SECOND = '0'	else	'Z';
 
 	INT_REG <= REG;
 
diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 215b980..a79c470 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -20,6 +20,10 @@ entity dhwk is
 --             SPC_RDY_IN : In    std_logic;
              TAST_RESn : In    std_logic;
              TAST_SETn : In    std_logic;
+             LED_2 : out    std_logic;
+             LED_3 : out    std_logic;
+             LED_4 : out    std_logic;
+             LED_5 : out    std_logic;
               PCI_AD : InOut std_logic_vector (31 downto 0);
              PCI_PAR : InOut std_logic;
              PCI_DEVSELn : Out   std_logic;
@@ -86,6 +90,7 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_IN : std_logic;
    signal SERIAL_OUT : std_logic;
    signal SPC_RDY_OUT : std_logic;
+   signal watch : std_logic;
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -219,6 +224,11 @@ end component;
 begin
 	SERIAL_IN <= SERIAL_OUT;
 	SPC_RDY_IN <= SPC_RDY_OUT;
+	LED_2 <= TAST_RESn;
+	LED_3 <= TAST_SETn;
+	LED_4 <= '0';
+	LED_5 <= not watch;
+	PCI_INTAn <= watch;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -239,7 +249,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );
+                 INTAn=>INTAn, PCI_INTAn=>watch);
    I14 : FIFO_CONTROL
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,