From: sithglan <sithglan>
Date: Sun, 11 Mar 2007 08:02:23 +0000 (+0000)
Subject: move address register
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/d452afd57d3469271a8532a9271ed7c14a53a427?ds=sidebyside

move address register
---

diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
index dc48107..d4233c6 100644
--- a/dhwk/dhwk.prj
+++ b/dhwk/dhwk.prj
@@ -18,7 +18,6 @@ vhdl work "source/Io_mux.vhd"
 vhdl work "source/CONT_FSM.vhd"
 vhdl work "source/COMM_FSM.vhd"
 vhdl work "source/COMM_DEC.vhd"
-vhdl work "source/Addr_regi.vhd"
 vhdl work "source/vergleich.vhd"
 vhdl work "source/steuerung.vhd"
 vhdl work "source/reg_io.vhd"
@@ -40,3 +39,4 @@ vhdl work "source/MESS_1_TB.vhd"
 vhdl work "source/INTERRUPT.vhd"
 vhdl work "source/top.vhd"
 vhdl work "source/ven_rev_id.vhd"
+vhdl work "source/pci/address_register.vhd"
diff --git a/dhwk/source/Addr_regi.vhd b/dhwk/source/Addr_regi.vhd
deleted file mode 100644
index 143c7b5..0000000
--- a/dhwk/source/Addr_regi.vhd
+++ /dev/null
@@ -1,43 +0,0 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: ADDR_REG.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity ADDR_REGI is
-	port
-	(
-	PCI_CLOCK			:in		std_logic;
-	PCI_RSTn			:in		std_logic;
-	LOAD_ADDR_REG	:in		std_logic;
-	AD_REG				:in		std_logic_vector (31 downto 0);
-	ADDR_REG			:out	std_logic_vector (31 downto 0)
-  );
-end entity ADDR_REGI;
-
-architecture ADDR_REGI_DESIGN of ADDR_REGI is
-
-	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
-
-begin 
-
-	process (PCI_CLOCK, PCI_RSTn) 
-	begin
-		if	PCI_RSTn = '0'	then	REG_ADDR	<= X"00000000";
-
-		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
-
-			if LOAD_ADDR_REG = '1' then
-						REG_ADDR	<=	AD_REG;
-
-			else	REG_ADDR	<=	REG_ADDR;
-			end if;
-
-		end if;
-	end process;
-
-	ADDR_REG	<=	REG_ADDR;
-
-end architecture ADDR_REGI_DESIGN;
diff --git a/dhwk/source/io_mux_reg.vhd b/dhwk/source/io_mux_reg.vhd
index 38f2356..564d8bb 100644
--- a/dhwk/source/io_mux_reg.vhd
+++ b/dhwk/source/io_mux_reg.vhd
@@ -38,7 +38,7 @@ architecture SCHEMATIC of IO_MUX_REG is
    signal  IO_DATA : std_logic_vector (31 downto 0);
    signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
 
-   component ADDR_REGI
+   component ADDRESS_REGISTER
       Port (  AD_REG : In    std_logic_vector (31 downto 0);
              LOAD_ADDR_REG : In    std_logic;
              PCI_CLOCK : In    std_logic;
@@ -77,7 +77,7 @@ begin
 
    AD_REG <= AD_REG_DUMMY;
 
-   I5 : ADDR_REGI
+   I5 : ADDRESS_REGISTER
       Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                  LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
                  PCI_RSTn=>PCI_RSTn,
diff --git a/dhwk/source/pci/address_register.vhd b/dhwk/source/pci/address_register.vhd
new file mode 100644
index 0000000..11602a9
--- /dev/null
+++ b/dhwk/source/pci/address_register.vhd
@@ -0,0 +1,39 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: ADDR_REG.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ADDRESS_REGISTER is
+	port (
+                PCI_CLOCK	:in	std_logic;
+                PCI_RSTn	:in	std_logic;
+                LOAD_ADDR_REG	:in	std_logic;
+                AD_REG		:in	std_logic_vector (31 downto 0);
+                ADDR_REG	:out	std_logic_vector (31 downto 0)
+        );
+end entity ADDRESS_REGISTER;
+
+architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
+	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
+begin 
+
+	process (PCI_CLOCK, PCI_RSTn) 
+	begin
+		if	PCI_RSTn = '0'	then
+                        REG_ADDR	<= X"00000000";
+
+		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+			if LOAD_ADDR_REG = '1' then
+                                REG_ADDR	<=	AD_REG;
+			else
+                                REG_ADDR	<=	REG_ADDR;
+			end if;
+		end if;
+	end process;
+
+	ADDR_REG	<=	REG_ADDR;
+
+end architecture ADDR_REGI_DESIGN;