From: sithglan Date: Mon, 19 Mar 2007 16:44:04 +0000 (+0000) Subject: lot of new files X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/e00b64cc5780386174db7506cad5bccee09087b0?ds=inline lot of new files --- diff --git a/ethernet/Makefile b/ethernet/Makefile new file mode 100644 index 0000000..d02d65d --- /dev/null +++ b/ethernet/Makefile @@ -0,0 +1,3 @@ +PROJECT := ethernet + +include ../common/Makefile.common diff --git a/ethernet/ethernet.prj b/ethernet/ethernet.prj new file mode 100644 index 0000000..5bd7d4e --- /dev/null +++ b/ethernet/ethernet.prj @@ -0,0 +1,28 @@ +vhdl work "source/top.vhd" +verilog work "source/ethernet/eth_crc.v" +verilog work "source/ethernet/eth_cop.v" +verilog work "source/ethernet/eth_maccontrol.v" +verilog work "source/ethernet/eth_register.v" +verilog work "source/ethernet/eth_fifo.v" +verilog work "source/ethernet/eth_rxstatem.v" +verilog work "source/ethernet/eth_txcounters.v" +verilog work "source/ethernet/eth_random.v" +verilog work "source/ethernet/eth_rxcounters.v" +verilog work "source/ethernet/eth_top.v" +verilog work "source/ethernet/eth_shiftreg.v" +verilog work "source/ethernet/eth_miim.v" +verilog work "source/ethernet/eth_wishbone.v" +verilog work "source/ethernet/eth_rxaddrcheck.v" +verilog work "source/ethernet/xilinx_dist_ram_16x32.v" +verilog work "source/ethernet/eth_spram_256x32.v" +verilog work "source/ethernet/eth_txethmac.v" +verilog work "source/ethernet/timescale.v" +verilog work "source/ethernet/eth_registers.v" +verilog work "source/ethernet/eth_defines.v" +verilog work "source/ethernet/eth_rxethmac.v" +verilog work "source/ethernet/eth_receivecontrol.v" +verilog work "source/ethernet/eth_outputcontrol.v" +verilog work "source/ethernet/eth_txstatem.v" +verilog work "source/ethernet/eth_transmitcontrol.v" +verilog work "source/ethernet/eth_macstatus.v" +verilog work "source/ethernet/eth_clockgen.v" diff --git a/ethernet/ethernet.ucf b/ethernet/ethernet.ucf new file mode 100644 index 0000000..b0b7d52 --- /dev/null +++ b/ethernet/ethernet.ucf @@ -0,0 +1,85 @@ +# NET "PCI_AD<0>" LOC = "A5" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<10>" LOC = "E9" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<11>" LOC = "F11" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<12>" LOC = "E10" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<13>" LOC = "A8" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<14>" LOC = "B9" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<15>" LOC = "B10" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<16>" LOC = "F17" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<17>" LOC = "F16" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<18>" LOC = "A14" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<19>" LOC = "B14" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<1>" LOC = "B5" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<20>" LOC = "B15" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<21>" LOC = "A15" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<22>" LOC = "F12" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<23>" LOC = "F13" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<24>" LOC = "D15" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<25>" LOC = "E15" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<26>" LOC = "D17" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<27>" LOC = "C17" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<28>" LOC = "B17" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<29>" LOC = "E17" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<2>" LOC = "E6" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<30>" LOC = "A18" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<31>" LOC = "B18" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<3>" LOC = "D6" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<4>" LOC = "C6" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<5>" LOC = "B6" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<6>" LOC = "D7" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<7>" LOC = "E7" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<8>" LOC = "B8" | IOSTANDARD = PCI33_3 ; +# NET "PCI_AD<9>" LOC = "F10" | IOSTANDARD = PCI33_3 ; +NET "PCI_CLOCK" LOC = "A11" | IOSTANDARD = PCI33_3 ; +# NET "PCI_IDSEL" LOC = "D14" | IOSTANDARD = PCI33_3 ; +# NET "PCI_CBEn<0>" LOC = "F9" | IOSTANDARD = PCI33_3 ; +# NET "PCI_CBEn<1>" LOC = "C10" | IOSTANDARD = PCI33_3 ; +# NET "PCI_CBEn<2>" LOC = "D13" | IOSTANDARD = PCI33_3 ; +# NET "PCI_CBEn<3>" LOC = "E13" | IOSTANDARD = PCI33_3 ; +# NET "PCI_FRAMEn" LOC = "C13" | IOSTANDARD = PCI33_3 ; +# NET "PCI_IRDYn" LOC = "A13" | IOSTANDARD = PCI33_3 ; +# NET "PCI_RSTn" LOC = "A19" | IOSTANDARD = PCI33_3 ; +# NET "PCI_DEVSELn" LOC = "E12" | IOSTANDARD = PCI33_3 ; +# NET "PCI_INTAn" LOC = "B19" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_PERRn" LOC = "D12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_SERRn" LOC = "B12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_STOPn" LOC = "A12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_TRDYn" LOC = "B13" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_REQn" LOC = "C18" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +# NET "PCI_GNTn" LOC = "D18" | IOSTANDARD = PCI33_3 ; +# NET "TAST_RESn" LOC = "AA3" | IOSTANDARD = LVTTL | PULLUP ; +# NET "TAST_SETn" LOC = "Y4" | IOSTANDARD = LVTTL | PULLUP ; +# NET "LED_2" LOC = "AB5" | IOSTANDARD = LVTTL | DRIVE = 24 ; +# NET "LED_3" LOC = "AA5" | IOSTANDARD = LVTTL | DRIVE = 24 ; +# NET "LED_4" LOC = "AA4" | IOSTANDARD = LVTTL | DRIVE = 24 ; +# NET "LED_5" LOC = "AB4" | IOSTANDARD = LVTTL | DRIVE = 24 ; +# NET "KONST_1" LOC = "Y1" | IOSTANDARD = LVCMOS33 ; +# NET "TB_IDSEL" LOC = "M6" | IOSTANDARD = LVCMOS33 ; +# NET "TB_nDEVSEL" LOC = "M5" | IOSTANDARD = LVCMOS33 ; +# NET "TB_nINTA" LOC = "U2" | IOSTANDARD = LVCMOS33 ; + +NET "MTX_CLK_PAD_I" LOC = "M2" | IOSTANDARD = LVCMOS33; + +NET "MTXD_PAD_O<0>" LOC = "M5" | IOSTANDARD = LVCMOS33; +NET "MTXD_PAD_O<1>" LOC = "M6" | IOSTANDARD = LVCMOS33; +NET "MTXD_PAD_O<2>" LOC = "T2" | IOSTANDARD = LVCMOS33; +NET "MTXD_PAD_O<3>" LOC = "T1" | IOSTANDARD = LVCMOS33; + +NET "MTXEN_PAD_O" LOC = "M1" | IOSTANDARD = LVCMOS33; +# NET "MTXERR_PAD_O" LOC = "" | IOSTANDARD = LVCMOS33; + +NET "MRX_CLK_PAD_I" LOC = "L1" | IOSTANDARD = LVCMOS33; + +NET "MRXD_PAD_I<0>" LOC = "N3" | IOSTANDARD = LVCMOS33; +NET "MRXD_PAD_I<1>" LOC = "N4" | IOSTANDARD = LVCMOS33; +NET "MRXD_PAD_I<2>" LOC = "V4" | IOSTANDARD = LVCMOS33; +NET "MRXD_PAD_I<3>" LOC = "V3" | IOSTANDARD = LVCMOS33; + +NET "MRXDV_PAD_I" LOC = "L2" | IOSTANDARD = LVCMOS33; +NET "MRXERR_PAD_I" LOC = "N1" | IOSTANDARD = LVCMOS33; + +NET "MCOLL_PAD_I" LOC = "N2" | IOSTANDARD = LVCMOS33; +NET "MCRS_PAD_I" LOC = "U3" | IOSTANDARD = LVCMOS33; +NET "MD_PAD_IO" LOC = "Y1" | IOSTANDARD = LVCMOS33; +NET "MDC_PAD_O" LOC = "U2" | IOSTANDARD = LVCMOS33; diff --git a/ethernet/ethernet.xst b/ethernet/ethernet.xst new file mode 100644 index 0000000..a68148a --- /dev/null +++ b/ethernet/ethernet.xst @@ -0,0 +1,51 @@ +set -xsthdpdir ./xst +run +-ifn ethernet.prj +-ifmt mixed +-ofn ethernet +-ofmt NGC +-p xc3s1500-fg456-4 +-top ethernet +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso ethernet.lso +-keep_hierarchy NO +-glob_opt AllClockNets +-rtlview Yes +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-mux_extract YES +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-equivalent_register_removal YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-slice_utilization_ratio_maxmargin 5