From: sithglan Date: Tue, 20 Mar 2007 22:17:38 +0000 (+0000) Subject: += use xilinx block ram for ethernet X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/e252c592d45f49f3c9e8a769caebca7db3378bce?ds=sidebyside += use xilinx block ram for ethernet --- diff --git a/ethernet/source/ethernet/eth_defines.v b/ethernet/source/ethernet/eth_defines.v index 26001f5..aaad999 100644 --- a/ethernet/source/ethernet/eth_defines.v +++ b/ethernet/source/ethernet/eth_defines.v @@ -41,8 +41,11 @@ // CVS Revision History // // $Log: eth_defines.v,v $ -// Revision 1.1 2007-03-20 17:50:56 sithglan -// add shit +// Revision 1.2 2007-03-20 22:17:38 sithglan +// += use xilinx block ram for ethernet +// +// Revision 1.1 2007/03/19 16:44:04 sithglan +// lot of new files // // Revision 1.34 2005/02/21 12:48:06 igorm // Warning fixes. @@ -186,7 +189,7 @@ `define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus // Ethernet implemented in Xilinx Chips (uncomment following lines) -// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo +`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo // `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors // Core is going to be implemented in Virtex FPGA and contains Virtex // specific elements.