From: sithglan Date: Sun, 11 Mar 2007 13:23:11 +0000 (+0000) Subject: perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/e687cadb7cace489b9920e045cd19ceb2ae8b01d?ds=sidebyside perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd --- diff --git a/dhwk/source/par_ser_con.vhd b/dhwk/source/par_ser_con.vhd index 2f183d9..92a01c0 100644 --- a/dhwk/source/par_ser_con.vhd +++ b/dhwk/source/par_ser_con.vhd @@ -1,4 +1,4 @@ --- $Id: par_ser_con.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $ +-- $Id: par_ser_con.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $ library ieee; use ieee.std_logic_1164.all; @@ -43,7 +43,7 @@ begin process(PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if ("0000" < COUNT) then COUNT <= COUNT - 1; end if; @@ -115,7 +115,7 @@ begin process(PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then SYNC <= SPC_RDY_IN; end if; end process; diff --git a/dhwk/source/pci/address_register.vhd b/dhwk/source/pci/address_register.vhd index 99360c5..56c480e 100644 --- a/dhwk/source/pci/address_register.vhd +++ b/dhwk/source/pci/address_register.vhd @@ -25,7 +25,7 @@ begin if PCI_RSTn = '0' then REG_ADDR <= X"00000000"; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then if LOAD_ADDR_REG = '1' then REG_ADDR <= AD_REG; else diff --git a/dhwk/source/pci/comm_dec.vhd b/dhwk/source/pci/comm_dec.vhd index c28d222..2cd7beb 100644 --- a/dhwk/source/pci/comm_dec.vhd +++ b/dhwk/source/pci/comm_dec.vhd @@ -89,7 +89,7 @@ begin process (PCI_CLOCK, PCI_RSTn) begin if PCI_RSTn = '0' then FRAME_REG_REGn <= '1'; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then FRAME_REG_REGn <= FRAME_REGn; diff --git a/dhwk/source/pci/comm_fsm.vhd b/dhwk/source/pci/comm_fsm.vhd index 82ecece..7735128 100644 --- a/dhwk/source/pci/comm_fsm.vhd +++ b/dhwk/source/pci/comm_fsm.vhd @@ -63,7 +63,7 @@ begin if PCI_RSTn = '0' then COMM_STATE <= "0000"; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then case COMM_STATE is when ST_IDLE_COMM => if IO_READ = '1' then COMM_STATE <= ST_IO_READ; diff --git a/dhwk/source/pci/config_04h.vhd b/dhwk/source/pci/config_04h.vhd index 70d0c9f..5e26083 100644 --- a/dhwk/source/pci/config_04h.vhd +++ b/dhwk/source/pci/config_04h.vhd @@ -52,7 +52,7 @@ begin CONF_STATUS(30) <= '0'; CONF_STATUS(31) <= '0'; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); @@ -92,7 +92,7 @@ begin CONF_COMMAND(15 downto 8) <= (others =>'0'); CONF_COMMAND( 6 downto 0) <= (others =>'0'); - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); diff --git a/dhwk/source/pci/config_10h.vhd b/dhwk/source/pci/config_10h.vhd index ad55b17..4660c6f 100644 --- a/dhwk/source/pci/config_10h.vhd +++ b/dhwk/source/pci/config_10h.vhd @@ -38,7 +38,7 @@ begin if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0'); - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24); diff --git a/dhwk/source/pci/config_3Ch.vhd b/dhwk/source/pci/config_3Ch.vhd index 2c79f4f..00d93eb 100644 --- a/dhwk/source/pci/config_3Ch.vhd +++ b/dhwk/source/pci/config_3Ch.vhd @@ -47,7 +47,7 @@ begin if PCI_RSTn = '0' then CONF_INT_LINE <= (others => '0'); - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0); end if; diff --git a/dhwk/source/pci/connecting_fsm.vhd b/dhwk/source/pci/connecting_fsm.vhd index eb444ea..421132f 100644 --- a/dhwk/source/pci/connecting_fsm.vhd +++ b/dhwk/source/pci/connecting_fsm.vhd @@ -66,7 +66,7 @@ begin process (PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if SIG_LOAD = '1' then REG <= S_FIFO_Q_OUT; @@ -82,7 +82,7 @@ begin process (PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if RESET = '1' then STATES <= S0; diff --git a/dhwk/source/pci/cont_fsm.vhd b/dhwk/source/pci/cont_fsm.vhd index 4600784..7ebd4c0 100644 --- a/dhwk/source/pci/cont_fsm.vhd +++ b/dhwk/source/pci/cont_fsm.vhd @@ -88,7 +88,7 @@ begin begin if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then case CONTROL_STATE is when ST_IDLE => diff --git a/dhwk/source/pci/fifo_io_control.vhd b/dhwk/source/pci/fifo_io_control.vhd index 03f914a..be85395 100644 --- a/dhwk/source/pci/fifo_io_control.vhd +++ b/dhwk/source/pci/fifo_io_control.vhd @@ -1,4 +1,4 @@ --- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $ +-- $Id: fifo_io_control.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $ library IEEE; use IEEE.std_logic_1164.all; @@ -35,7 +35,7 @@ begin process (PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if (RESET = '1') then S_FIFO_WRITEn <= '1'; SIG_S_ERROR <= '0'; diff --git a/dhwk/source/pci/flag_bus.vhd b/dhwk/source/pci/flag_bus.vhd index 2b3c654..5e6ba02 100644 --- a/dhwk/source/pci/flag_bus.vhd +++ b/dhwk/source/pci/flag_bus.vhd @@ -46,7 +46,7 @@ begin process (PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then FF1_S_EFn <= not S_EFn; FF1_S_HFn <= not S_HFn; FF1_S_FFn <= not S_FFn; @@ -59,7 +59,7 @@ begin process (PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if HOLD = '0' then FF2_S_EFn <= FF1_S_EFn; FF2_S_HFn <= FF1_S_HFn; diff --git a/dhwk/source/pci/interrupt.vhd b/dhwk/source/pci/interrupt.vhd index a3709b6..5d3b473 100644 --- a/dhwk/source/pci/interrupt.vhd +++ b/dhwk/source/pci/interrupt.vhd @@ -75,7 +75,7 @@ begin FF_A <= "00000000"; FF_B <= "00000000"; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then if (RESET = '1') then SET <= "00000000"; FF_A <= "00000000"; @@ -105,7 +105,7 @@ begin if (PCI_RSTn = '0') then REG <= "00000000"; - elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif(rising_edge(PCI_CLOCK)) then if(RESET = '1') then REG <= "00000000"; @@ -132,7 +132,7 @@ begin process (PCI_CLOCK) begin - if(PCI_CLOCK'event and PCI_CLOCK = '1') then + if(rising_edge(PCI_CLOCK)) then SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT; end if; end process; diff --git a/dhwk/source/pci/io_reg.vhd b/dhwk/source/pci/io_reg.vhd index ecbd9d6..3003c36 100644 --- a/dhwk/source/pci/io_reg.vhd +++ b/dhwk/source/pci/io_reg.vhd @@ -49,7 +49,7 @@ begin REG_IDSEL <= '0'; REG_PAR <= '0'; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then REG_AD <= IO_DATA; REG_CBEn <= PCI_CBEn; REG_FRAMEn <= PCI_FRAMEn; diff --git a/dhwk/source/pci/parity_out.vhd b/dhwk/source/pci/parity_out.vhd index c8ecfa7..e169ba3 100644 --- a/dhwk/source/pci/parity_out.vhd +++ b/dhwk/source/pci/parity_out.vhd @@ -44,7 +44,7 @@ begin PERR_FF <= '0'; SERR_FF <= '0'; - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + elsif (rising_edge(PCI_CLOCK)) then SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF); PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF); end if; diff --git a/dhwk/source/ser_par_con.vhd b/dhwk/source/ser_par_con.vhd index d68124d..6c45577 100644 --- a/dhwk/source/ser_par_con.vhd +++ b/dhwk/source/ser_par_con.vhd @@ -1,4 +1,4 @@ --- $Id: ser_par_con.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $ +-- $Id: ser_par_con.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $ library ieee; use ieee.std_logic_1164.all; @@ -46,7 +46,7 @@ begin process(PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if ("0000" < COUNT) then COUNT <= COUNT - 1; end if; @@ -129,7 +129,7 @@ begin process(PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn; end if; end process; @@ -137,7 +137,7 @@ begin process(PCI_CLOCK) begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if (rising_edge(PCI_CLOCK)) then if (RESET = '1') then STARTBIT <= "0000"; else