From: sithglan <sithglan>
Date: Sun, 11 Mar 2007 10:54:47 +0000 (+0000)
Subject: merge config space
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/e90b12fe13402c4c3e6935acf0b09fedecf18fd0

merge config space
---

diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
index e8c63b7..90b7114 100644
--- a/dhwk/dhwk.prj
+++ b/dhwk/dhwk.prj
@@ -4,7 +4,6 @@ vhdl work "source/pci/address_register.vhd"
 vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
 vhdl work "source/pci/config_04h.vhd"
-vhdl work "source/pci/config_08h.vhd"
 vhdl work "source/pci/config_10h.vhd"
 vhdl work "source/pci/config_3Ch.vhd"
 vhdl work "source/pci/config_mux_0.vhd"
diff --git a/dhwk/source/pci/config_08h.vhd b/dhwk/source/pci/config_08h.vhd
deleted file mode 100644
index 7b19df6..0000000
--- a/dhwk/source/pci/config_08h.vhd
+++ /dev/null
@@ -1,28 +0,0 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONFIG_08H.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity CONFIG_08H is
-        port
-        (
-                REVISION_ID :in std_logic_vector ( 7 downto 0);
-                CONF_DATA_08H :out std_logic_vector (31 downto 0)
-        );
-end entity CONFIG_08H;
-
-architecture CONFIG_08H_DESIGN of CONFIG_08H is
-
- -- PCI Configuration Space Header Addr : HEX 08 --
-
-        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";--other comm. device
-        --constant CONF_REVISION_ID :std_logic_vector ( 7 downto 0) := X"00";
-
-begin
-
-        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
-
-end architecture CONFIG_08H_DESIGN;
diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index de57983..0cd1420 100644
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -28,6 +28,8 @@ end CONFIG_SPACE_HEADER;
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
         constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
+        --other comm. device
+        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
 
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
@@ -86,11 +88,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
         end component;
 
-        component CONFIG_08H
-                Port ( REVISION_ID : In std_logic_vector (7 downto 0);
-                       CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
-        end component;
-
         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
@@ -104,6 +101,7 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
 begin
         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
+        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
         CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
@@ -137,9 +135,6 @@ begin
         CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
         PCI_RSTn=>PCI_RSTn,
         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
-        I4 : CONFIG_08H
-        Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
-        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),