From: michael <michael>
Date: Sat, 10 Mar 2007 16:41:30 +0000 (+0000)
Subject: irgendwie gehts
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/f822acebac284df723c5196d47295f447c5338df

irgendwie gehts
---

diff --git a/dhwk/source/CONT_FSM.vhd b/dhwk/source/CONT_FSM.vhd
index 67fc8a7..025c1e7 100644
--- a/dhwk/source/CONT_FSM.vhd
+++ b/dhwk/source/CONT_FSM.vhd
@@ -57,7 +57,7 @@ architecture CONT_FSM_DESIGN of CONT_FSM is
 	constant	ST_READ_3			:std_logic_vector (9 downto 0) := "0100111111" ;-- 13F
 
 	constant	ST_RD_FIFO_1	:std_logic_vector (9 downto 0) := "0000110011" ;-- 033
-	constant	ST_RD_FIFO_2	:std_logic_vector (9 downto 0) := "1000110011" ;-- 233
+	constant	ST_RD_FIFO_2	:std_logic_vector (9 downto 0) := "1100110011" ;-- 233
 
 
 	constant	ST_WRITE_1		:std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2
diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 1c2d52e..9a93404 100644
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -44,7 +44,8 @@ entity FIFO_CONTROL is
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
              SYNC_FLAG : Out   std_logic_vector (7 downto 0);
-	     PAR_SER_IN : Out std_logic_vector (7 downto 0));
+	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
+	     SER_PAR_OUT : Out std_logic_vector (7 downto 0));
 end FIFO_CONTROL;
 
 architecture SCHEMATIC of FIFO_CONTROL is
@@ -56,6 +57,7 @@ architecture SCHEMATIC of FIFO_CONTROL is
    signal XXXS_FIFO_READn : std_logic;
    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
+   signal watcher : std_logic_vector (7 downto 0);
 
    component SER_PAR_CON
       Port ( PCI_CLOCK : In    std_logic;
@@ -129,14 +131,15 @@ begin
 
    SYNC_FLAG <= SYNC_FLAG_DUMMY;
    PAR_SER_IN <= S_FIFO_Q_OUT;
-
+   SER_PAR_OUT <= watcher;
+   R_FIFO_D_IN(7 downto 0) <= watcher;
 
    RESERVE <= gnd;
    I23 : SER_PAR_CON
       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
-                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
+                 PAR_OUT(7 downto 0)=>watcher,
                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
    I22 : PAR_SER_CON
       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c..2d25fcd 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -170,6 +170,7 @@ architecture SCHEMATIC of dhwk is
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
 	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
+	     SER_PAR_OUT : Out std_logic_vector (7 downto 0);
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
    end component;
 
@@ -251,7 +252,7 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, others => '0');
+	trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
 	data(0) <= watch;
 	
 	data(1) <= R_EFn;
@@ -272,6 +273,7 @@ begin
 	data(16) <= SPC_RDY_IN;
 	data(17) <= SERIAL_OUT;
 	data(18) <= SPC_RDY_OUT;
+	data(34 downto 27) <= R_FIFO_Q_OUT;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,