From: sithglan <sithglan>
Date: Sun, 11 Mar 2007 10:50:27 +0000 (+0000)
Subject: begin to merge confi space
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/ffdaba18b3414c86a37889c31ced80a16676f3f4?ds=inline

begin to merge confi space
---

diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
index 113fec6..e8c63b7 100644
--- a/dhwk/dhwk.prj
+++ b/dhwk/dhwk.prj
@@ -3,7 +3,6 @@ vhdl work "source/ser_par_con.vhd"
 vhdl work "source/pci/address_register.vhd"
 vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
-vhdl work "source/pci/config_00h.vhd"
 vhdl work "source/pci/config_04h.vhd"
 vhdl work "source/pci/config_08h.vhd"
 vhdl work "source/pci/config_10h.vhd"
diff --git a/dhwk/source/pci/config_00h.vhd b/dhwk/source/pci/config_00h.vhd
deleted file mode 100644
index 98b4532..0000000
--- a/dhwk/source/pci/config_00h.vhd
+++ /dev/null
@@ -1,28 +0,0 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONFIG_00H.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity CONFIG_00H is
-        port
-        (
-                VENDOR_ID :in std_logic_vector (15 downto 0);
-                CONF_DATA_00H :out std_logic_vector (31 downto 0)
-        );
-end entity CONFIG_00H;
-
-architecture CONFIG_00H_DESIGN of CONFIG_00H is
-
- -- PCI Configuration Space Header Addr : HEX 00 --
-
-        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--????
-        --constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--????
-
-begin
-
-        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
-
-end architecture CONFIG_00H_DESIGN;
diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index 15db761..de57983 100644
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -27,6 +27,8 @@ end CONFIG_SPACE_HEADER;
 
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
+        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
+
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -89,11 +91,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
         end component;
 
-        component CONFIG_00H
-                Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
-                       CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
-        end component;
-
         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
@@ -106,6 +103,7 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         end component;
 
 begin
+        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
         CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
@@ -142,9 +140,6 @@ begin
         I4 : CONFIG_08H
         Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
         CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
-        I3 : CONFIG_00H
-        Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
-        CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),