From 0de2df9caee0439ffcd042c82921a4e4753de8c3 Mon Sep 17 00:00:00 2001 From: sithglan Date: Sun, 11 Feb 2007 22:24:57 +0000 Subject: [PATCH] -= comments --- dhwk_old/source/top_dhwk.vhd | 58 ------------------------------------ 1 file changed, 58 deletions(-) diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd index 98add0f..67fe5aa 100644 --- a/dhwk_old/source/top_dhwk.vhd +++ b/dhwk_old/source/top_dhwk.vhd @@ -1,43 +1,8 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: top.vhd | ---| | ---| Components: pci32lite.vhd | ---| pciwbsequ.vhd | ---| pcidmux.vhd | ---| pciregs.vhd | ---| pcipargen.vhd | ---| -- Libs -- | ---| ona.vhd | ---| | ---| Description: RS1 PCI Demo : (TOP) Main file. | ---| | ---| | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ - - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - entity dhwk is port ( @@ -69,17 +34,9 @@ port ( end dhwk; ---+-----------------------------------------------------------------------------+ ---| ARCHITECTURE | ---+-----------------------------------------------------------------------------+ - architecture dhwk_arch of dhwk is ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ - component pci32tlite port ( @@ -170,13 +127,6 @@ port ( end component; ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - signal wb_adr : std_logic_vector(24 downto 1); signal wb_dat_out : std_logic_vector(15 downto 0); signal wb_dat_in : std_logic_vector(15 downto 0); @@ -191,10 +141,6 @@ end component; begin ---+-----------------------------------------+ ---| PCI Target | ---+-----------------------------------------+ - u_pci: component pci32tlite port map( clk33 => PCI_CLK, @@ -225,10 +171,6 @@ port map( -- debug_access => LED2 ); ---+-----------------------------------------+ ---| WB-7seg | ---+-----------------------------------------+ - my_heartbeat: component heartbeat port map( clk_i => PCI_CLK, -- 2.39.5