From 27f6f6203a7917361c6b1e482b03ab69c0e428a2 Mon Sep 17 00:00:00 2001 From: sithglan Date: Tue, 20 Mar 2007 20:33:59 +0000 Subject: [PATCH 1/1] progress --- ethernet/ethernet.prj | 173 ++++++++++++++++----------------- ethernet/ethernet.ucf | 1 - ethernet/source/top.vhd | 205 ++++++++++++++++++++++++---------------- 3 files changed, 208 insertions(+), 171 deletions(-) diff --git a/ethernet/ethernet.prj b/ethernet/ethernet.prj index 8b9a454..9086799 100644 --- a/ethernet/ethernet.prj +++ b/ethernet/ethernet.prj @@ -1,86 +1,87 @@ -vhdl work "source/ethernet/eth_crc.v" -vhdl work "source/ethernet/eth_cop.v" -vhdl work "source/ethernet/eth_maccontrol.v" -vhdl work "source/ethernet/eth_register.v" -vhdl work "source/ethernet/eth_fifo.v" -vhdl work "source/ethernet/eth_rxstatem.v" -vhdl work "source/ethernet/eth_txcounters.v" -vhdl work "source/ethernet/eth_random.v" -vhdl work "source/ethernet/eth_rxcounters.v" -vhdl work "source/ethernet/eth_top.v" -vhdl work "source/ethernet/eth_shiftreg.v" -vhdl work "source/ethernet/eth_miim.v" -vhdl work "source/ethernet/eth_wishbone.v" -vhdl work "source/ethernet/eth_rxaddrcheck.v" -vhdl work "source/ethernet/xilinx_dist_ram_16x32.v" -vhdl work "source/ethernet/eth_spram_256x32.v" -vhdl work "source/ethernet/eth_txethmac.v" -vhdl work "source/ethernet/timescale.v" -vhdl work "source/ethernet/eth_registers.v" -vhdl work "source/ethernet/eth_defines.v" -vhdl work "source/ethernet/eth_rxethmac.v" -vhdl work "source/ethernet/eth_receivecontrol.v" -vhdl work "source/ethernet/eth_outputcontrol.v" -vhdl work "source/ethernet/eth_txstatem.v" -vhdl work "source/ethernet/eth_transmitcontrol.v" -vhdl work "source/ethernet/eth_macstatus.v" -vhdl work "source/ethernet/eth_clockgen.v" -vhdl work "source/pci/pci_target_unit.v" -vhdl work "source/pci/pci_target32_stop_crit.v" -vhdl work "source/pci/pci_delayed_sync.v" -vhdl work "source/pci/pci_wb_slave_unit.v" -vhdl work "source/pci/pci_frame_load_crit.v" -vhdl work "source/pci/pci_mas_ad_en_crit.v" -vhdl work "source/pci/pci_constants.v" -vhdl work "source/pci/pci_wbw_wbr_fifos.v" -vhdl work "source/pci/pci_wb_slave.v" -vhdl work "source/pci/pci_target32_trdy_crit.v" -vhdl work "source/pci/pci_target32_interface.v" -vhdl work "source/pci/pci_wbw_fifo_control.v" -vhdl work "source/pci/pci_wb_tpram.v" -vhdl work "source/pci/pci_par_crit.v" -vhdl work "source/pci/pci_conf_space.v" -vhdl work "source/pci/pci_target32_sm.v" -vhdl work "source/pci/pci_pciw_pcir_fifos.v" -vhdl work "source/pci/pci_serr_en_crit.v" -vhdl work "source/pci/pci_target32_devs_crit.v" -vhdl work "source/pci/pci_out_reg.v" -vhdl work "source/pci/pci_mas_ad_load_crit.v" -vhdl work "source/pci/pci_delayed_write_reg.v" -vhdl work "source/pci/pci_wbs_wbb3_2_wbb2.v" -vhdl work "source/pci/pci_wb_master.v" -vhdl work "source/pci/bus_commands.v" -vhdl work "source/pci/pci_rst_int.v" -vhdl work "source/pci/pci_sync_module.v" -vhdl work "source/pci/pci_master32_sm_if.v" -vhdl work "source/pci/pci_frame_crit.v" -vhdl work "source/pci/pci_user_constants.v" -vhdl work "source/pci/pci_io_mux_ad_load_crit.v" -vhdl work "source/pci/pci_pciw_fifo_control.v" -vhdl work "source/pci/pci_parity_check.v" -vhdl work "source/pci/pci_irdy_out_crit.v" -vhdl work "source/pci/pci_perr_crit.v" -vhdl work "source/pci/pci_mas_ch_state_crit.v" -vhdl work "source/pci/pci_spoci_ctrl.v" -vhdl work "source/pci/pci_wb_addr_mux.v" -vhdl work "source/pci/pci_perr_en_crit.v" -vhdl work "source/pci/pci_target32_clk_en.v" -vhdl work "source/pci/timescale.v" -vhdl work "source/pci/pci_serr_crit.v" -vhdl work "source/pci/pci_frame_en_crit.v" -vhdl work "source/pci/pci_master32_sm.v" -vhdl work "source/pci/pci_pci_tpram.v" -vhdl work "source/pci/pci_cur_out_reg.v" -vhdl work "source/pci/pci_io_mux.v" -vhdl work "source/pci/pci_wbr_fifo_control.v" -vhdl work "source/pci/pci_ram_16x40d.v" -vhdl work "source/pci/pci_io_mux_ad_en_crit.v" -vhdl work "source/pci/pci_async_reset_flop.v" -vhdl work "source/pci/pci_wb_decoder.v" -vhdl work "source/pci/pci_conf_cyc_addr_dec.v" -vhdl work "source/pci/pci_bridge32.v" -vhdl work "source/pci/pci_synchronizer_flop.v" -vhdl work "source/pci/pci_pcir_fifo_control.v" -vhdl work "source/pci/pci_cbe_en_crit.v" -vhdl work "source/pci/pci_pci_decoder.v" -vhdl work "source/pci/pci_in_reg.v" +verilog work "source/ethernet/eth_crc.v" +verilog work "source/ethernet/eth_cop.v" +verilog work "source/ethernet/eth_maccontrol.v" +verilog work "source/ethernet/eth_register.v" +verilog work "source/ethernet/eth_fifo.v" +verilog work "source/ethernet/eth_rxstatem.v" +verilog work "source/ethernet/eth_txcounters.v" +verilog work "source/ethernet/eth_random.v" +verilog work "source/ethernet/eth_rxcounters.v" +verilog work "source/ethernet/eth_top.v" +verilog work "source/ethernet/eth_shiftreg.v" +verilog work "source/ethernet/eth_miim.v" +verilog work "source/ethernet/eth_wishbone.v" +verilog work "source/ethernet/eth_rxaddrcheck.v" +verilog work "source/ethernet/xilinx_dist_ram_16x32.v" +verilog work "source/ethernet/eth_spram_256x32.v" +verilog work "source/ethernet/eth_txethmac.v" +verilog work "source/ethernet/timescale.v" +verilog work "source/ethernet/eth_registers.v" +verilog work "source/ethernet/eth_defines.v" +verilog work "source/ethernet/eth_rxethmac.v" +verilog work "source/ethernet/eth_receivecontrol.v" +verilog work "source/ethernet/eth_outputcontrol.v" +verilog work "source/ethernet/eth_txstatem.v" +verilog work "source/ethernet/eth_transmitcontrol.v" +verilog work "source/ethernet/eth_macstatus.v" +verilog work "source/ethernet/eth_clockgen.v" +verilog work "source/pci/pci_target_unit.v" +verilog work "source/pci/pci_target32_stop_crit.v" +verilog work "source/pci/pci_delayed_sync.v" +verilog work "source/pci/pci_wb_slave_unit.v" +verilog work "source/pci/pci_frame_load_crit.v" +verilog work "source/pci/pci_mas_ad_en_crit.v" +verilog work "source/pci/pci_constants.v" +verilog work "source/pci/pci_wbw_wbr_fifos.v" +verilog work "source/pci/pci_wb_slave.v" +verilog work "source/pci/pci_target32_trdy_crit.v" +verilog work "source/pci/pci_target32_interface.v" +verilog work "source/pci/pci_wbw_fifo_control.v" +verilog work "source/pci/pci_wb_tpram.v" +verilog work "source/pci/pci_par_crit.v" +verilog work "source/pci/pci_conf_space.v" +verilog work "source/pci/pci_target32_sm.v" +verilog work "source/pci/pci_pciw_pcir_fifos.v" +verilog work "source/pci/pci_serr_en_crit.v" +verilog work "source/pci/pci_target32_devs_crit.v" +verilog work "source/pci/pci_out_reg.v" +verilog work "source/pci/pci_mas_ad_load_crit.v" +verilog work "source/pci/pci_delayed_write_reg.v" +verilog work "source/pci/pci_wbs_wbb3_2_wbb2.v" +verilog work "source/pci/pci_wb_master.v" +verilog work "source/pci/bus_commands.v" +verilog work "source/pci/pci_rst_int.v" +verilog work "source/pci/pci_sync_module.v" +verilog work "source/pci/pci_master32_sm_if.v" +verilog work "source/pci/pci_frame_crit.v" +verilog work "source/pci/pci_user_constants.v" +verilog work "source/pci/pci_io_mux_ad_load_crit.v" +verilog work "source/pci/pci_pciw_fifo_control.v" +verilog work "source/pci/pci_parity_check.v" +verilog work "source/pci/pci_irdy_out_crit.v" +verilog work "source/pci/pci_perr_crit.v" +verilog work "source/pci/pci_mas_ch_state_crit.v" +verilog work "source/pci/pci_spoci_ctrl.v" +verilog work "source/pci/pci_wb_addr_mux.v" +verilog work "source/pci/pci_perr_en_crit.v" +verilog work "source/pci/pci_target32_clk_en.v" +verilog work "source/pci/timescale.v" +verilog work "source/pci/pci_serr_crit.v" +verilog work "source/pci/pci_frame_en_crit.v" +verilog work "source/pci/pci_master32_sm.v" +verilog work "source/pci/pci_pci_tpram.v" +verilog work "source/pci/pci_cur_out_reg.v" +verilog work "source/pci/pci_io_mux.v" +verilog work "source/pci/pci_wbr_fifo_control.v" +verilog work "source/pci/pci_ram_16x40d.v" +verilog work "source/pci/pci_io_mux_ad_en_crit.v" +verilog work "source/pci/pci_async_reset_flop.v" +verilog work "source/pci/pci_wb_decoder.v" +verilog work "source/pci/pci_conf_cyc_addr_dec.v" +verilog work "source/pci/pci_bridge32.v" +verilog work "source/pci/pci_synchronizer_flop.v" +verilog work "source/pci/pci_pcir_fifo_control.v" +verilog work "source/pci/pci_cbe_en_crit.v" +verilog work "source/pci/pci_pci_decoder.v" +verilog work "source/pci/pci_in_reg.v" +vhdl work "source/top.vhd" diff --git a/ethernet/ethernet.ucf b/ethernet/ethernet.ucf index 3ad2942..2850ebf 100644 --- a/ethernet/ethernet.ucf +++ b/ethernet/ethernet.ucf @@ -49,7 +49,6 @@ NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ; NET "PCI_REQn" LOC = "C18" | IOSTANDARD = PCI33_3 | SLEW = FAST ; NET "PCI_GNTn" LOC = "D18" | IOSTANDARD = PCI33_3 ; -NET "INT_CLOCK" LOC = "AA11" | IOSTANDARD = PCI33_3 ; NET "MTX_CLK_PAD_I" LOC = "M2" | IOSTANDARD = LVCMOS33; NET "MTXD_PAD_O<0>" LOC = "M5" | IOSTANDARD = LVCMOS33; diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index af81bdd..0541222 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -1,4 +1,7 @@ -entity top is +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +entity ethernet is PORT( PCI_AD : INOUT std_logic_vector(31 downto 0); PCI_CLOCK : IN std_logic; @@ -27,11 +30,11 @@ PORT( MCOLL_PAD_I : IN std_logic; MCRS_PAD_I : IN std_logic; MD_PAD_IO : INOUT std_logic; - MDC_PAD_O : OUT std_logic; + MDC_PAD_O : OUT std_logic ); -end top; +end ethernet; -architecture bla of top is +architecture ethernet_arch of ethernet is COMPONENT eth_top PORT( @@ -169,57 +172,91 @@ signal pci_perr_o : std_logic; signal pci_perr_oe_o : std_logic; signal pci_serr_o : std_logic; signal pci_serr_oe_o : std_logic; -signal pci_ad_oe_o : std_logic; -signal pci_cbe_oe_o : std_logic; +signal pci_ad_oe_o : std_logic_vector(31 downto 0); +signal pci_cbe_oe_o : std_logic_vector(3 downto 0); signal pci_ad_o : std_logic_vector (31 downto 0); signal pci_cbe_o : std_logic_vector (3 downto 0); +signal wb_clk_i : std_logic; +signal wb_rst_i : std_logic; +signal wb_dat_i : std_logic_vector (31 downto 0); +signal wb_dat_o : std_logic_vector (31 downto 0); +signal wb_adr_i : std_logic_vector (11 downto 2); +signal wb_sel_i : std_logic_vector (3 downto 0); +signal wb_we_i : std_logic; +signal wb_cyc_i : std_logic; +signal wb_stb_i : std_logic; +signal wb_ack_o : std_logic; +signal wb_err_o : std_logic; +signal m_wb_adr_o : std_logic_vector(31 downto 0); +signal m_wb_sel_o : std_logic_vector(3 downto 0); +signal m_wb_we_o : std_logic; +signal m_wb_dat_o : std_logic_vector(31 downto 0); +signal m_wb_dat_i : std_logic_vector(31 downto 0); +signal m_wb_cyc_o : std_logic; +signal m_wb_stb_o : std_logic; +signal m_wb_ack_i : std_logic; +signal m_wb_err_i : std_logic; +signal md_pad_o : std_logic; +signal md_padoe_o : std_logic; +signal int_o : std_logic; +signal wbm_adr_o : std_logic_vector(31 downto 0); + BEGIN -PCI_RSTn <= if (pci_rst_oe_o = '1') then pci_rst_o else 'Z'; -PCI_INTAn <= if (pci_inta_oe_o = '1') then pci_inta_o else 'Z'; -PCI_REQn <= if (pci_req_oe_o = '1') then pci_req_o else 'Z'; -PCI_FRAMEn <= if (pci_frame_oe_o '1') then pci_frame_o else 'Z'; -PCI_IRDYn <= if (pci_irdy_oe_o = '1') then pci_irdy_o else 'Z'; -PCI_DEVSELn <= if (pci_devsel_oe_o = '1') then pci_devsel_o else 'Z'; -PCI_TRDYn <= if (pci_trdy_oe_o = '1') then pci_trdy_o else 'Z'; -PCI_STOPn <= if (pci_stop_oe_o = '1') then pci_stop_o else 'Z'; -PCI_AD <= if (pci_ad_oe_o = '1') then pci_ad_o else (others => 'Z'); -PCI_CBEn <= if (pci_cbe_oe_o = '1') then pci_cbe_o else (others => 'Z'); -PCI_PAR <= if (pci_par_oe_o = '1') then pci_par_o else 'Z'; -PCI_PERRn <= if (pci_perr_oe_o = '1') then pci_perr_o else 'Z'; -PCI_SERRn <= if (pci_serr_oe_o = '1') then pci_serr_o else 'Z'; +PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; +PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z'; +PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z'; +PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z'; +PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z'; +PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z'; +PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z'; +PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z'; +PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z'; +PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z'; +PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z'; +MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z'; + +BLA1: FOR i in 31 downto 0 generate +PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z'; +end generate; + +BLA2: FOR i in 3 downto 0 generate +PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z'; +end generate; + +wb_adr_i <= wbm_adr_o (11 downto 2); Inst_pci_bridge32: pci_bridge32 PORT MAP( - wb_clk_i => , - wb_rst_i => , - wb_rst_o => , - wb_int_i => , - wb_int_o => , - wbs_adr_i => , - wbs_dat_i => , - wbs_dat_o => , - wbs_sel_i => , - wbs_cyc_i => , - wbs_stb_i => , - wbs_we_i => , - wbs_cti_i => , - wbs_bte_i => , - wbs_ack_o => , - wbs_rty_o => , - wbs_err_o => , - wbm_adr_o => , - wbm_dat_i => , - wbm_dat_o => , - wbm_sel_o => , - wbm_cyc_o => , - wbm_stb_o => , - wbm_we_o => , - wbm_cti_o => , - wbm_bte_o => , - wbm_ack_i => , - wbm_rty_i => , - wbm_err_i => , + wb_clk_i => wb_clk_i , + wb_rst_i => '0', + wb_rst_o => wb_rst_i, + wb_int_i => int_o, + -- wb_int_o => , + wbs_adr_i => m_wb_adr_o , + wbs_dat_i => m_wb_dat_o, + wbs_dat_o => m_wb_dat_i, + wbs_sel_i => m_wb_sel_o, + wbs_cyc_i => m_wb_cyc_o, + wbs_stb_i => m_wb_stb_o, + wbs_we_i => m_wb_we_o, + wbs_cti_i => (others => '0'), + wbs_bte_i => (others => '0'), + wbs_ack_o => m_wb_ack_i, + -- wbs_rty_o => , + wbs_err_o => m_wb_err_i, + wbm_adr_o => wbm_adr_o, + wbm_dat_i => wb_dat_o, + wbm_dat_o => wb_dat_i, + wbm_sel_o => wb_sel_i, + wbm_cyc_o => wb_cyc_i, + wbm_stb_o => wb_stb_i, + wbm_we_o => wb_we_i, + -- wbm_cti_o => , + -- wbm_bte_o => , + wbm_ack_i => wb_ack_o , + wbm_rty_i => '0', + wbm_err_i => wb_err_o, pci_clk_i => PCI_CLOCK, pci_rst_i => PCI_RSTn, pci_rst_o => pci_rst_o , @@ -263,41 +300,41 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( ); Inst_eth_top: eth_top PORT MAP( - wb_clk_i => , - wb_rst_i => , - wb_dat_i => , - wb_dat_o => , - wb_adr_i => , - wb_sel_i => , - wb_we_i => , - wb_cyc_i => , - wb_stb_i => , - wb_ack_o => , - wb_err_o => , - m_wb_adr_o => , - m_wb_sel_o => , - m_wb_we_o => , - m_wb_dat_o => , - m_wb_dat_i => , - m_wb_cyc_o => , - m_wb_stb_o => , - m_wb_ack_i => , - m_wb_err_i => , - mtx_clk_pad_i => , - mtxd_pad_o => , - mtxen_pad_o => , - mtxerr_pad_o => , - mrx_clk_pad_i => , - mrxd_pad_i => , - mrxdv_pad_i => , - mrxerr_pad_i => , - mcoll_pad_i => , - mcrs_pad_i => , - mdc_pad_o => , - md_pad_i => , - md_pad_o => , - md_padoe_o => , - int_o => + wb_clk_i => wb_clk_i , + wb_rst_i => wb_rst_i , + wb_dat_i => wb_dat_i , + wb_dat_o => wb_dat_o , + wb_adr_i => wb_adr_i , + wb_sel_i => wb_sel_i , + wb_we_i => wb_we_i , + wb_cyc_i => wb_cyc_i , + wb_stb_i => wb_stb_i , + wb_ack_o => wb_ack_o , + wb_err_o => wb_err_o , + m_wb_adr_o => m_wb_adr_o, + m_wb_sel_o => m_wb_sel_o, + m_wb_we_o => m_wb_we_o , + m_wb_dat_o => m_wb_dat_o, + m_wb_dat_i => m_wb_dat_i, + m_wb_cyc_o => m_wb_cyc_o, + m_wb_stb_o => m_wb_stb_o, + m_wb_ack_i => m_wb_ack_i, + m_wb_err_i => m_wb_err_i, + mtx_clk_pad_i => MTX_CLK_PAD_I, + mtxd_pad_o => MTXD_PAD_O, + mtxen_pad_o => MTXEN_PAD_O, + -- mtxerr_pad_o => , + mrx_clk_pad_i => MRX_CLK_PAD_I, + mrxd_pad_i => MRXD_PAD_I, + mrxdv_pad_i => MRXDV_PAD_I, + mrxerr_pad_i => MRXERR_PAD_I, + mcoll_pad_i => MCOLL_PAD_I, + mcrs_pad_i => MCRS_PAD_I, + mdc_pad_o => MDC_PAD_O, + md_pad_i => MD_PAD_IO, + md_pad_o => md_pad_o, + md_padoe_o => md_padoe_o, + int_o => int_o ); -end architecture bla; +end architecture ethernet_arch; -- 2.39.5