From 2825d08e6e5a5c0ba429f454065da84d6623cf9f Mon Sep 17 00:00:00 2001 From: michael Date: Sat, 10 Mar 2007 12:34:55 +0000 Subject: [PATCH] fifo --- dhwk/source/FLAG_BUS.vhd | 12 +++---- dhwk/source/top.vhd | 74 ++++++++++++++++++++++++++++++---------- 2 files changed, 62 insertions(+), 24 deletions(-) diff --git a/dhwk/source/FLAG_BUS.vhd b/dhwk/source/FLAG_BUS.vhd index c312be7..dd95bb2 100644 --- a/dhwk/source/FLAG_BUS.vhd +++ b/dhwk/source/FLAG_BUS.vhd @@ -48,12 +48,12 @@ begin begin if (PCI_CLOCK'event and PCI_CLOCK = '1') then - FF1_S_EFn <= S_EFn; - FF1_S_HFn <= S_HFn; - FF1_S_FFn <= S_FFn; - FF1_R_EFn <= R_EFn; - FF1_R_HFn <= R_HFn; - FF1_R_FFn <= R_FFn; + FF1_S_EFn <= not S_EFn; + FF1_S_HFn <= not S_HFn; + FF1_S_FFn <= not S_FFn; + FF1_R_EFn <= not R_EFn; + FF1_R_HFn <= not R_HFn; + FF1_R_FFn <= not R_FFn; end if; end process; diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd index e0ad093..3036632 100644 --- a/dhwk/source/top.vhd +++ b/dhwk/source/top.vhd @@ -16,14 +16,6 @@ entity dhwk is PCI_IDSEL : In std_logic; PCI_IRDYn : In std_logic; PCI_RSTn : In std_logic; - R_EFn : In std_logic; - R_FFn : In std_logic; - R_FIFO_Q_OUT : In std_logic_vector (7 downto 0); - R_HFn : In std_logic; - S_EFn : In std_logic; - S_FFn : In std_logic; - S_FIFO_Q_OUT : In std_logic_vector (7 downto 0); - S_HFn : In std_logic; SERIAL_IN : In std_logic; SPC_RDY_IN : In std_logic; TAST_RESn : In std_logic; @@ -36,16 +28,6 @@ entity dhwk is PCI_SERRn : Out std_logic; PCI_STOPn : Out std_logic; PCI_TRDYn : Out std_logic; - R_FIFO_D_IN : Out std_logic_vector (7 downto 0); - R_FIFO_READn : Out std_logic; - R_FIFO_RESETn : Out std_logic; - R_FIFO_RTn : Out std_logic; - R_FIFO_WRITEn : Out std_logic; - S_FIFO_D_IN : Out std_logic_vector (7 downto 0); - S_FIFO_READn : Out std_logic; - S_FIFO_RESETn : Out std_logic; - S_FIFO_RTn : Out std_logic; - S_FIFO_WRITEn : Out std_logic; SERIAL_OUT : Out std_logic; SPC_RDY_OUT : Out std_logic; TB_IDSEL : Out std_logic; @@ -82,6 +64,24 @@ architecture SCHEMATIC of dhwk is signal READ_SEL : std_logic_vector (1 downto 0); signal AD_REG : std_logic_vector (31 downto 0); signal REG_OUT_XX7 : std_logic_vector (7 downto 0); + signal R_EFn : std_logic; + signal R_FFn : std_logic; + signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0); + signal R_HFn : std_logic; + signal S_EFn : std_logic; + signal S_FFn : std_logic; + signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0); + signal S_HFn : std_logic; + signal R_FIFO_D_IN : std_logic_vector (7 downto 0); + signal R_FIFO_READn : std_logic; + signal R_FIFO_RESETn : std_logic; + signal R_FIFO_RTn : std_logic; + signal R_FIFO_WRITEn : std_logic; + signal S_FIFO_D_IN : std_logic_vector (7 downto 0); + signal S_FIFO_READn : std_logic; + signal S_FIFO_RESETn : std_logic; + signal S_FIFO_RTn : std_logic; + signal S_FIFO_WRITEn : std_logic; component MESS_1_TB Port ( DEVSELn : In std_logic; @@ -197,6 +197,21 @@ architecture SCHEMATIC of dhwk is WRITE_XX7_6 : Out std_logic ); end component; +component fifo_generator_v3_2 + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + almost_empty: OUT std_logic; + almost_full: OUT std_logic; + dout: OUT std_logic_VECTOR(7 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_full: OUT std_logic); +end component; + begin I19 : MESS_1_TB @@ -267,4 +282,27 @@ begin WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 ); +receive_fifo : fifo_generator_v3_2 + port map ( + clk => PCI_CLOCK, + din => R_FIFO_D_IN, + rd_en => not R_FIFO_READn, + rst => not R_FIFO_RESETn, + wr_en => not R_FIFO_WRITEn, + dout => R_FIFO_Q_OUT, + empty => R_EFn, + full => R_FFn, + prog_full => R_HFn); + +send_fifo : fifo_generator_v3_2 + port map ( + clk => PCI_CLOCK, + din => S_FIFO_D_IN, + rd_en => not S_FIFO_READn, + rst => not S_FIFO_RESETn, + wr_en => not S_FIFO_WRITEn, + dout => S_FIFO_Q_OUT, + empty => S_EFn, + full => S_FFn, + prog_full => S_HFn); end SCHEMATIC; -- 2.39.5