From 2e92b1a116510750a30acf463cbe53ef2f0e8648 Mon Sep 17 00:00:00 2001 From: sithglan Date: Sun, 11 Mar 2007 11:34:00 +0000 Subject: [PATCH 1/1] cleanup config space --- dhwk/dhwk.prj | 1 - dhwk/source/pci/config_rd_0.vhd | 134 ------------------------ dhwk/source/pci/config_space_header.vhd | 45 +++++--- 3 files changed, 30 insertions(+), 150 deletions(-) delete mode 100644 dhwk/source/pci/config_rd_0.vhd diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj index 45171bc..9b412ff 100644 --- a/dhwk/dhwk.prj +++ b/dhwk/dhwk.prj @@ -3,7 +3,6 @@ vhdl work "source/ser_par_con.vhd" vhdl work "source/pci/address_register.vhd" vhdl work "source/pci/comm_dec.vhd" vhdl work "source/pci/comm_fsm.vhd" -vhdl work "source/pci/config_rd_0.vhd" vhdl work "source/pci/config_space_header.vhd" vhdl work "source/pci/connecting_fsm.vhd" vhdl work "source/pci/cont_fsm.vhd" diff --git a/dhwk/source/pci/config_rd_0.vhd b/dhwk/source/pci/config_rd_0.vhd deleted file mode 100644 index 92b6a98..0000000 --- a/dhwk/source/pci/config_rd_0.vhd +++ /dev/null @@ -1,134 +0,0 @@ --- J.STELZNER --- INFORMATIK-3 LABOR --- 23.08.2006 --- File: CONFIG_RD_0.VHD - -library IEEE; -use IEEE.std_logic_1164.all; - -entity CONFIG_RD_0 is - port - ( - ADDR_REG :in std_logic_vector (31 downto 0); - CF_RD_COM :in std_logic; - READ_SEL :out std_logic_vector ( 2 downto 0) - ); -end entity CONFIG_RD_0; - -architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is - - -- - -- - -- - -- - -- - -- PCI Configuration Space Header - -- - -- \ Bit - -- \ - --Address |31 24|23 16|15 8|7 0| - ----------------------------------------------------------------- - --00 |Device ID |Vendor ID | - --04 |Status |Command | - --08 |Class Code |Revision ID| - --0C |BIST |Header Type|Latency T. |Cache L.S. | - --10-24 |Base Address Register | - --28 |Cardbus CIS Pointer | - --2C |Subsystem ID |Subsystem Vendor ID | - --30 |Expansion ROM Base Address | - --34 |Reserved | - --38 |Reserved | - --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line | - --40-FF | | - ----------------------------------------------------------------- - - - --PCI Bus Commands - --C/BE[3..0] Command Type - -------------------------------------- - -- 0000 Interrupt Acknowledge - -- 0001 Special Cycle - -- 0010 I/O Read - -- 0011 I/O Write - -- 0100 Reserved - -- 0101 Reserved - -- 0110 Memory Read - -- 0111 Memory Write - -- - -- 1000 Reserved - -- 1001 Reserved - -- 1010 Configuration Read - -- 1011 Configuration Write - -- 1100 Memory Read Multiple - -- 1101 Dual Address Cycle - -- 1110 Memory Read Line - -- 1111 Memory Write and Invalidate - - - --PCI Byte Enable - --C/BE[3..0] gueltige Datenbits - ------------------------------- - -- 0000 AD 31..0 - -- 1000 AD 23..0 - -- 1100 AD 15..0 - -- 1110 AD 7..0 - - constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000"; - constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001"; - constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010"; - constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011"; - constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100"; - constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101"; - constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110"; - constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111"; - constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000"; - constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001"; - constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010"; - constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011"; - constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100"; - constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101"; - constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110"; - constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111"; - - signal MUX :std_logic_vector(31 downto 0); - signal CONFIG_ADDR :std_logic_vector( 7 downto 0); - -begin - - CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0); - - --******************************************************************* - --*********************** PCI Read Address ************************** - --******************************************************************* - - process (CF_RD_COM, CONFIG_ADDR) - begin - - if CF_RD_COM = '1' then - if CONFIG_ADDR = X"00" then - READ_SEL <= "000"; - - elsif CONFIG_ADDR = X"04" then - READ_SEL <= "001"; - - elsif CONFIG_ADDR = X"08" then - READ_SEL <= "010"; - - elsif CONFIG_ADDR = X"10" then - READ_SEL <= "011"; - - elsif CONFIG_ADDR = X"3C" then - READ_SEL <= "100"; - - elsif CONFIG_ADDR = X"40" then - READ_SEL <= "101"; - - else - READ_SEL <= "111"; - end if; - else - READ_SEL <= "111"; - end if; - end process; - -end architecture CONFIG_RD_0_DESIGN; diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd index 0b98174..363e4c1 100644 --- a/dhwk/source/pci/config_space_header.vhd +++ b/dhwk/source/pci/config_space_header.vhd @@ -112,9 +112,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is signal CONFIG_ADDR :std_logic_vector(7 downto 0); signal CONFIG_WRITE :std_logic_vector(3 downto 0); - ---- - ---- - SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; @@ -122,17 +119,10 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is signal CONF_WR_10H : std_logic; signal CONF_WR_3CH : std_logic; signal CONF_READ_SEL : std_logic_vector (2 downto 0); - signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0); signal CONF_DATA_3CH : std_logic_vector (31 downto 0); signal CONF_DATA_08H : std_logic_vector (31 downto 0); signal CONF_DATA_00H : std_logic_vector (31 downto 0); - component CONFIG_RD_0 - Port ( ADDR_REG : In std_logic_vector (31 downto 0); - CF_RD_COM : In std_logic; - READ_SEL : Out std_logic_vector (2 downto 0) ); - end component; - begin CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; @@ -152,11 +142,6 @@ begin CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE CONF_DATA_10H <= CONF_BAS_ADDR_REG; - I9 : CONFIG_RD_0 - Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), - CF_RD_COM=>CF_RD_COM, - READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) ); - process (PCI_CLOCK,PCI_RSTn) begin if PCI_RSTn = '0' then @@ -328,4 +313,34 @@ begin CONF_WR_3CH <= CONFIG_WRITE(2); --CONF_WR_40H <= CONFIG_WRITE(3); + process (CF_RD_COM, CONFIG_ADDR) + begin + + if CF_RD_COM = '1' then + if CONFIG_ADDR = X"00" then + CONF_READ_SEL <= "000"; + + elsif CONFIG_ADDR = X"04" then + CONF_READ_SEL <= "001"; + + elsif CONFIG_ADDR = X"08" then + CONF_READ_SEL <= "010"; + + elsif CONFIG_ADDR = X"10" then + CONF_READ_SEL <= "011"; + + elsif CONFIG_ADDR = X"3C" then + CONF_READ_SEL <= "100"; + + elsif CONFIG_ADDR = X"40" then + CONF_READ_SEL <= "101"; + + else + CONF_READ_SEL <= "111"; + end if; + else + CONF_READ_SEL <= "111"; + end if; + end process; + end SCHEMATIC; -- 2.39.5