From 675f45d062971a8e9a17be7aa2f19b102d60c7b0 Mon Sep 17 00:00:00 2001 From: michael Date: Wed, 21 Mar 2007 14:01:16 +0000 Subject: [PATCH] a bit better --- ethernet/phydcm.xaw | 2 +- ethernet/source/phydcm.vhd | 34 +++++++++++----------------------- ethernet/source/top.vhd | 8 +++----- 3 files changed, 15 insertions(+), 29 deletions(-) diff --git a/ethernet/phydcm.xaw b/ethernet/phydcm.xaw index 262cfc5..573e496 100644 --- a/ethernet/phydcm.xaw +++ b/ethernet/phydcm.xaw @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.4e 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3c==;1v>?50;0x915=;916>:490:&2g?4?3ty=h7>51z?77?0d3-5<5s4>86?;4=35917=z{:>1<7>6s|5883>4}:<:0>46*9e;43?xu403:1=v3<5;43?!0b2?:0q~<7:183!0b2?:0qp`=6;295~{i:>0;6{|l1e?6=9rwe>o4?:0y~j7e=83;pqc85927;7415uIJIw=sO@Qy~DE \ No newline at end of file diff --git a/ethernet/source/phydcm.vhd b/ethernet/source/phydcm.vhd index efec74a..a5db448 100644 --- a/ethernet/source/phydcm.vhd +++ b/ethernet/source/phydcm.vhd @@ -7,7 +7,7 @@ -- \ \ \/ Version : 9.1.02i -- \ \ Application : xaw2vhdl -- / / Filename : phydcm.vhd --- /___/ /\ Timestamp : 03/21/2007 14:47:39 +-- /___/ /\ Timestamp : 03/21/2007 14:56:33 -- \ \ / \ -- \___\/\___\ -- @@ -26,30 +26,23 @@ library UNISIM; use UNISIM.Vcomponents.ALL; entity phydcm is - port ( CLKIN_IN : in std_logic; - RST_IN : in std_logic; - CLKFX_OUT : out std_logic; - CLKIN_IBUFG_OUT : out std_logic; - CLK0_OUT : out std_logic; - LOCKED_OUT : out std_logic); + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); end phydcm; architecture BEHAVIORAL of phydcm is - signal CLKFB_IN : std_logic; - signal CLKFX_BUF : std_logic; - signal CLKIN_IBUFG : std_logic; - signal CLK0_BUF : std_logic; - signal GND_BIT : std_logic; + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; component BUFG port ( I : in std_logic; O : out std_logic); end component; - component IBUFG - port ( I : in std_logic; - O : out std_logic); - end component; - -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns component DCM @@ -91,16 +84,11 @@ architecture BEHAVIORAL of phydcm is begin GND_BIT <= '0'; - CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); - CLKIN_IBUFG_INST : IBUFG - port map (I=>CLKIN_IN, - O=>CLKIN_IBUFG); - CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); @@ -121,7 +109,7 @@ begin PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, - CLKIN=>CLKIN_IBUFG, + CLKIN=>CLKIN_IN, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 480de0a..1617eee 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -175,7 +175,6 @@ component phydcm is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; - CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end component; @@ -406,10 +405,9 @@ eth_dcm : phydcm port map ( CLKIN_IN => PCI_CLOCK, RST_IN => not PCI_RSTn, - CLKFX_OUT => PHY_CLOCK --- CLKIN_IBUFG_OUT --- CLK0_OUT --- LOCKED_OUT + CLKFX_OUT => PHY_CLOCK, + CLK0_OUT => open, + LOCKED_OUT => open ); end architecture ethernet_arch; -- 2.39.5